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There are three individual 2D [[mesh interconnect|mesh]] [[NoCs]]. A dedicated 2D mesh connects the L1 caches to the L2 caches, another 2D mesh connects the L2 caches to the L3 caches, and a third 2D mesh connects the L3 caches to the external memory. All three NoCs are extended from the chiplet through the interposer to the other chiplets. | There are three individual 2D [[mesh interconnect|mesh]] [[NoCs]]. A dedicated 2D mesh connects the L1 caches to the L2 caches, another 2D mesh connects the L2 caches to the L3 caches, and a third 2D mesh connects the L3 caches to the external memory. All three NoCs are extended from the chiplet through the interposer to the other chiplets. | ||
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== Base die == | == Base die == |
Facts about "TSARLET - Microarchitectures - CEA Leti"
codename | TSARLET + |
core count | 96 + |
designer | CEA-Leti + |
full page name | cea-leti/microarchitectures/tsarlet + |
instance of | microarchitecture + |
instruction set architecture | MIPS32v1 + |
manufacturer | STMicroelectronics + |
microarchitecture type | CPU + |
name | TSARLET + |
pipeline stages | 5 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) + |