Editing cavium/octeon tx/cn8020

{{cavium title|CN8020}}
{{chip
| name                = Octeon TX CN8020
| no image            = 
| image               = 
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = 
| model number        = 
| part number         = 
| part number 2       = 
| part number 3       = 
| part number 4       = 
| market              = Storage
| first announced     = 
| first launched      = 
| last order          = 
| last shipment       = 
| release price       = 

| family              = OCTEON TX
| series              = CN80xx
| locked              = 
| frequency           = 1,500MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = ARM
| isa                 = ArmV8
| microarch           = Armv8.1
| platform            = 
| chipset             = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 
| transistors         = 
| technology          = CMOS
| die area            = 
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 2
| thread count        = 2
| max cpus            = 1
| max memory          = 16GB
| max memory addr     = 

| electrical          = 
| power               = 
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
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| v io 3              = 
| sdp                 = 
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| tdp typical         = 
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| temp min            = 
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|package module 1=
}}
'''CN8020''' is a {{arch|64}} [[dual-core]] [[ARM]] processor designed by [[Cavium]]. This processor, which incorporates 2 {{cavium|thunderx1|l=arch}} cores. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as networking, TCP & [[QoS]], and crypto acceleration.

== Cache ==
{{main|cavium/microarchitectures/thunderx1|Cache}}
{{cache size
|l1 cache=208KiB
|l1i cache=144KiB
|l1i break=2x72 KiB
|l1d cache=64 KiB
|l1d break=2x32 KiB
|l2 cache=1 MiB
|l2 break=1x1 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR3/4-2100
|ecc=Yes
|max mem=16GB
|controllers=1
|channels=
|width=72bit
|max bandwidth=
|bandwidth schan=
|bandwidth dchan=
}}

== Expansions ==
{{expansions
}}

== Networking ==
Interface options:

{{network
}}

== Hardware Accelerators ==
{{accelerators
|security=Yes
|tcp=Yes
|qos=Yes
}}

== Block diagram ==

== Datasheet ==
* [https://www.marvell.com/documents/ob2v9t3r0eltazxb8lqb/|OCTEON CN80XX/CN81XX Processors Product Brief]
base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +
core count	2 +
designer	Cavium +
family	OCTEON TX +
full page name	cavium/octeon tx/cn8020 +
has ecc memory support	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	ArmV8 +
isa family	ARM +
l1$ size	208 KiB (212,992 B, 0.203 MiB) +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size	144 KiB (147,456 B, 0.141 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	1900 +
market segment	Storage +
max cpu count	1 +
microarchitecture	Armv8.1 +
name	Octeon TX CN8020 +
series	CN80xx +
smp max ways	1 +
supported memory type	DDR3/4-2100 +
technology	CMOS +
thread count	2 +
word size	64 bit (8 octets, 16 nibbles) +