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== Members == | == Members == | ||
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=== CN58xx Series === | === CN58xx Series === | ||
The CN58xx series come with [[4 cores|4]] to [[16 cores|16]] {{cavium|cnMIPS|l=arch}} cores. All models incorporate the following features: | The CN58xx series come with [[4 cores|4]] to [[16 cores|16]] {{cavium|cnMIPS|l=arch}} cores. All models incorporate the following features: | ||
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* Network interfaces support for up to 2x [[RGMII]] or 2x [[SPI-4.2]] | * Network interfaces support for up to 2x [[RGMII]] or 2x [[SPI-4.2]] | ||
* 72/144 bit DD2-800 memory | * 72/144 bit DD2-800 memory |
Facts about "OCTEON Plus - Cavium"
designer | Cavium + |
first announced | October 9, 2006 + |
first launched | February 2007 + |
full page name | cavium/octeon plus + |
instance of | system on a chip family + |
instruction set architecture | MIPS64 + |
main designer | Cavium + |
manufacturer | TSMC + |
microarchitecture | cnMIPS + |
name | Cavium OCTEON Plus + |
package | FCBGA-1521 + |
process | 90 nm (0.09 μm, 9.0e-5 mm) + |
socket | BGA-1521 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |