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| tambient max = | | tambient max = | ||
− | |package | + | | packaging = Yes |
+ | | package 0 = FCBGA-1521 | ||
+ | | package 0 type = FCBGA | ||
+ | | package 0 pins = 1521 | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
+ | | socket 0 = BGA-1521 | ||
+ | | socket 0 type = BGA | ||
}} | }} | ||
'''CN5830-800 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service microprocessor (NSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, [[RegEx]], compression/decompression, and TCP acceleration. | '''CN5830-800 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service microprocessor (NSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, [[RegEx]], compression/decompression, and TCP acceleration. |
Facts about "CN5830-800 NSP - Cavium"