Editing cavium/octeon

{{cavium title|OCTEON}}
{{ic family
| title             = Cavium OCTEON
| image             = octeon cn38xx.png
| caption           = CN38xx
| developer         = Cavium
| manufacturer      = TSMC
| type              = System on chips
| first announced   = September 13, 2004
| first launched    = June 1, 2005
| production start  = 
| production end    = 
| arch              = MIPS64 R2 network SoCs
| isa               = MIPS64
| microarch         = cnMIPS
| word              = 64 bit
| proc              = 130 nm
| tech              = CMOS
| clock min         = 400 MHz
| clock max         = 600 MHz
| package           = FCBGA-1521
| package 2         = HSBGA-868
| socket            = BGA-1521
| socket 2          = BGA-868

| succession       = Yes
| predecessor      = 
| predecessor link = 
| successor        = OCTEON II
| successor link   = cavium/octeon ii
}}
'''OCTEON''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] for networking devices.

== Overview ==
The original OCTEON family of network-oriented microprocessors were announced in September of [[2004]]. These chips are based on [[Cavium]]'s newly announced microarchitecture, {{cavium|cnMIPS|l=arch}}, announced the same day. The cnMIPS design is a fully compliant {{mips|MIPS64}} revision 2 implementation. OCTEON chips are found in many enterprise an [[data center]] network servers, routers, and switches as well as various high-end residential routers.

== Architecture ==
{{main|cavium/microarchitectures/cnmips|l1=cnMIPS µarch}}
The cnMIPS microarchitecture is a [[fully-custom]] design implementing the {{mips|MIPS64}} revision 2 ISA on [[TSMC]]'s [[130 nm process]]. Due to the specific nature of the applicatons running, an [[FPU]] was omitted. Instead, Cavium opted to incorporate a wide array of hardware accelerators for network applications (L3 to L7) including support for compression/decompression algorithms (e.g.[[GZIP]]), and security/crypto algorithms (e.g. [[DES]], [[AES]], [[MD5]], and [[SHA1]]).

== Members ==

=== CN3000 Series ===
The CN3000 series is entry-level processors containing just one cnMIPS core. Depending on the option, these processors either have an array of security-related hardware accelerators (e.g. [[AES]], [[TRNG]]) or various communication accelerators (e.g. hardware packet I/O processing). Additionally, all models have 1-3 [[RGMII]] interfaces, [[Conventional PCI]] interface, and USB 2.0. The 3010 models also have an TDM/PCM interface for direct VoIP communication.
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
<table class="wikitable sortable tc10">
<tr><th colspan="10" style="background:#D6D6FF;">CN3000-Series Microprocessors</th></tr>
<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th></tr>
{{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3000]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?l2$ size#KiB
 |?power dissipation
 |?base frequency
 |?supported memory type
 |?max memory
 |?has ecc memory support
 |format=template
 |template=proc table 3
 |userparam=11:11
 |mainlabel=-
 |sort=model number
}}
{{table count|col=10|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3000]]}}
</table>

=== CN3100 Series ===
The CN3100 series includes both 110 and 120 models. Apart from their core count, they have an identical feature set which includes (depending on the version of the model chosen) an array of hardware accelerators for packet I/O processing, [[encryption]], [[TCP]], [[QoS]], compression/decompression, and [[RegEx]]. Additionally, these models support a faster [[PCI-X]] bus operating up to 100 MHz, gigabit Ethernet ([[GMII]]), and up to DDR2-667 ECC memory.
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
<table class="wikitable sortable">
<tr><th colspan="10" style="background:#D6D6FF;">CN3100-Series Microprocessors</th></tr>
<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th></tr>
{{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3100]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?l2$ size#KiB
 |?power dissipation
 |?base frequency
 |?supported memory type
 |?max memory
 |?has ecc memory support
 |format=template
 |template=proc table 3
 |userparam=11:11
 |mainlabel=-
 |sort=model number
}}
{{table count|col=10|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3100]]}}
</table>

== Datasheet ==
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]]
* [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]]
* [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX /CN36XX 4 to 16-Core Product Brief]]
designer	Cavium +
first announced	September 13, 2004 +
first launched	June 1, 2005 +
full page name	cavium/octeon +
instance of	system on a chip family +
instruction set architecture	MIPS64 +
main designer	Cavium +
manufacturer	TSMC +
microarchitecture	cnMIPS +
name	Cavium OCTEON +
package	FCBGA-1521 + and HSBGA-868 +
process	130 nm (0.13 μm, 1.3e-4 mm) +
socket	BGA-1521 + and BGA-868 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +