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== Architecture == | == Architecture == | ||
{{main|cavium/microarchitectures/cnmips|l1=cnMIPS µarch}} | {{main|cavium/microarchitectures/cnmips|l1=cnMIPS µarch}} | ||
− | The cnMIPS microarchitecture is a [[fully-custom]] design implementing the {{mips|MIPS64}} revision 2 ISA on [[TSMC]]'s [[130 nm process]]. Due to the specific nature of the applicatons running, an [[FPU]] was omitted. Instead, Cavium opted to | + | The cnMIPS microarchitecture is a [[fully-custom]] design implementing the {{mips|MIPS64}} revision 2 ISA on [[TSMC]]'s [[130 nm process]]. Due to the specific nature of the applicatons running, an [[FPU]] was omitted. Instead, Cavium opted to incorporated a wide array of hardware accelerators for network applications (L3 to L7) including support for compression/decompression algorithms (e.g.[[GZIP]]), and security/crypto algorithms (e.g. [[DES]], [[AES]], [[MD5]], and [[SHA1]]). |
== Members == | == Members == |
Facts about "OCTEON - Cavium"
designer | Cavium + |
first announced | September 13, 2004 + |
first launched | June 1, 2005 + |
full page name | cavium/octeon + |
instance of | system on a chip family + |
instruction set architecture | MIPS64 + |
main designer | Cavium + |
manufacturer | TSMC + |
microarchitecture | cnMIPS + |
name | Cavium OCTEON + |
package | FCBGA-1521 + and HSBGA-868 + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
socket | BGA-1521 + and BGA-868 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |