Editing cavium/octeon/cn3120-500bg868-exp

{{cavium title|CN3120-500 EXP}}
{{chip
| name                = Cavium CN3120-500 EXP
| no image            = 
| image               = octeon cn31xx.png
| image size          = 
| caption             = 
| designer            = Cavium
| manufacturer        = TSMC
| model number        = CN3120-500 EXP
| part number         = CN3120-500BG868-EXP
| part number 2       = 
| part number 3       = 
| part number 4       = 
| market              = Embedded
| first announced     = January 30, 2006 
| first launched      = May 1, 2006
| last order          = 
| last shipment       = 
| release price       = 

| family              = OCTEON
| series              = CN3100
| locked              = 
| frequency           = 500 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    = 

| isa family          = MIPS
| isa                 = MIPS64
| microarch           = cnMIPS
| platform            = 
| chipset             = 
| core name           = cnMIPS
| core family         = 
| core model          = 
| core stepping       = 
| process             = 130 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 2
| thread count        = 2
| max cpus            = 1
| max memory          = 4 GiB
| max memory addr     = 

| electrical          = 
| power               = 
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = 
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = <!-- .. °C -->
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

|package module 1={{packages/cavium/hsbga-868}}
}}
The '''CN3120-500 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

== Cache ==
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
{{cache size
|l1 cache=80 KiB
|l1i cache=64 KiB
|l1i break=2x32 KiB
|l1i desc=4-way set associative
|l1d cache=16 KiB
|l1d break=2x8 KiB
|l1d desc=64-way set associative
|l1d policy=Write-through
|l2 cache=256 KiB
|l2 break=1x256 KiB
|l2 desc=8-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR2-667
|ecc=Yes
|max mem=4 GiB
|controllers=1
|channels=1
|width=64 bit
|max bandwidth=4.97 GiB/s
|bandwidth schan=4.97 GiB/s
}}

Optional low-latency controller for content-based processing and meta data

{{memory controller
|type=DDR2-667
|ecc=Yes
|max mem=2 GiB
|controllers=1
|channels=1
|width=16 bit
|max bandwidth=1.24 GiB/s
|bandwidth schan=1.24 GiB/s
}}

== Expansions ==
{{expansions
|pcix width=32 bit
|pcix clock=100 MHz
|pcix rate=381.5 MiB/s
|pci extra=host or slave
|usb revision=2.0
|usb ports=1
|usb rate=60 MB/s
|usb extra=host / PHY
|uart=yes
|uart ports=2
|gp io=Yes
}}

== Networking ==
{{network
|mii opts=Yes
|rgmii=yes
|rgmii ports=3
|gmii=yes
|gmii ports=1
|pcm=Yes
}}

== Hardware Accelerators ==
{{accelerators
|regex=Yes
|regex feature=8 Engines
|compression=Yes
|decompression=Yes
|tcp=Yes
|qos=Yes
}}

== Block diagram ==
[[File:octeon cn31xx block diagram.png|750px]]

== Datasheet ==
* [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN3120-500 EXP - Cavium#package +
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	2 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	January 30, 2006 +
first launched	May 1, 2006 +
full page name	cavium/octeon/cn3120-500bg868-exp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description	64-way set associative +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	8-way set associative +
l2$ size	0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldate	May 1, 2006 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth	4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3120-500 EXP +
name	Cavium CN3120-500 EXP +
package	HSBGA-868 +
part number	CN3120-500BG868-EXP +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3100 +
smp max ways	1 +
supported memory type	DDR2-667 +
technology	CMOS +
thread count	2 +
word size	64 bit (8 octets, 16 nibbles) +