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{{cavium title|CN3010-500 SCP}} | {{cavium title|CN3010-500 SCP}} | ||
− | {{ | + | {{mpu |
| name = Cavium CN3010-500 SCP | | name = Cavium CN3010-500 SCP | ||
| no image = | | no image = | ||
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| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3010 | + | | model number = CN3010 |
| part number = CN3010-500BG525-SCP | | part number = CN3010-500BG525-SCP | ||
+ | | part number 1 = | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
− | |||
| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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| max memory addr = | | max memory addr = | ||
− | + | | electrical = Yes | |
| power = 4 W | | power = 4 W | ||
| v core = | | v core = | ||
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}} | }} | ||
− | == | + | == Features == |
− | + | Hardware acceleration units: | |
− | + | * Hardware implementation for common security algorithms: | |
− | + | ** DES, 3DES, AES (up to 256 bit), SHA1, SHA-2 up to SHA-512, RSA, DH | |
− | + | * QoS | |
− | + | * TCP Acceleration | |
− | |||
== Block diagram == | == Block diagram == |
Facts about "CN3010-500 SCP - Cavium"
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
core count | 1 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3010-500bg525-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + |
ldate | May 1, 2006 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3010-500 SCP + |
name | Cavium CN3010-500 SCP + |
part number | CN3010-500BG525-SCP + |
power dissipation | 4 W (4,000 mW, 0.00536 hp, 0.004 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3000 + |
smp max ways | 1 + |
supported memory type | DDR2-533 + |
technology | CMOS + |
thread count | 1 + |
word size | 64 bit (8 octets, 16 nibbles) + |