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{{cavium title|CN3010-300 SCP}} | {{cavium title|CN3010-300 SCP}} | ||
− | {{ | + | {{mpu |
| name = Cavium CN3010-300 SCP | | name = Cavium CN3010-300 SCP | ||
| no image = | | no image = | ||
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| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3010 | + | | model number = CN3010 |
| part number = CN3010-300BG525-SCP | | part number = CN3010-300BG525-SCP | ||
+ | | part number 1 = | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
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| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
− | | release price = $ | + | | release price = $19 |
| family = OCTEON | | family = OCTEON | ||
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| max memory addr = | | max memory addr = | ||
− | + | | electrical = Yes | |
| power = 2 W | | power = 2 W | ||
| v core = | | v core = | ||
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}} | }} | ||
The '''CN3010-300 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-300bg350-scp|CN3005 equivalent}}, double DDR2 memory access, as well as support for TDM/PCM (VoIP support). | The '''CN3010-300 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-300bg350-scp|CN3005 equivalent}}, double DDR2 memory access, as well as support for TDM/PCM (VoIP support). | ||
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Facts about "CN3010-300 SCP - Cavium"
base frequency | 300 MHz (0.3 GHz, 300,000 kHz) + |
core count | 1 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3010-300bg525-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + |
ldate | May 1, 2006 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3010-300 SCP + |
name | Cavium CN3010-300 SCP + |
part number | CN3010-300BG525-SCP + |
power dissipation | 2 W (2,000 mW, 0.00268 hp, 0.002 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
release price | $ 39.00 (€ 35.10, £ 31.59, ¥ 4,029.87) + |
series | CN3000 + |
smp max ways | 1 + |
supported memory type | DDR2-533 + |
technology | CMOS + |
thread count | 1 + |
word size | 64 bit (8 octets, 16 nibbles) + |