Editing cavium/microarchitectures/cnmips

{{cavium title|cnMIPS|arch}}
{{microarchitecture
| atype         = CPU
| name          = cnMIPS
| designer      = Cavium
| manufacturer  = TSMC
| introduction  = September 13, 2004
| phase-out     = 
| process       = 130 nm
| cores         = 1
| cores         = 2
| cores 2       = 4
| core  3       = 6
| cores 4       = 8
| cores 5       = 10
| cores 6       = 12
| cores 7       = 16

| pipeline      = Yes
| type          = Superscalar
| type 2        = 
| type N        = 
| OoOE          = No
| speculative   = No
| renaming      = No
| stages        = 5
| issues        = 2

| inst          = Yes
| isa           = MIPS64
| feature       = 
| extension     = 
| extension 2   = 

| cache         = Yes
| l1i           = 32 KiB
| l1i per       = core
| l1i desc      = 64-way set associative
| l1d           = 8-16 KiB
| l1d per       = core
| l1d desc      = 8-way set associative
| l2            = 1-2 MiB
| l2 per        = chip
| l2 desc       = 8-way set associative
| l3            = 
| l3 per        = 
| l3 desc       = 

| core names       = Yes
| core name        = cnMIPS

| succession       = Yes
| predecessor      = 
| predecessor link = 
| successor        = cnMIPS II
| successor link   = cavium/microarchitectures/cnmips_ii
}}
'''cnMIPS''' or '''cnMIPS64''' is the first [[microarchitecture]] implementing the {{mips|MIPS64}} ISA designed by [[Cavium]] for their {{cavium|Octeon}} family of processors. The "cn" stands for "Cavium Networks" or "content networking". This microarchitecture was designed with network-related applications (L3 through L7) in mind which resulted in a large selection of hardware accelerators (compression/security) being included.

== History ==
The cnMIPS was [[Cavium]]'s first [[microarchitecture]] developed completely in-house from the ground up. The cnMIPS is also the first implementation of the {{mips|MIPS64|MIPS64 Release 2}} ISA. The design was done by a group of 35 engineers who previously worked on [[DEC]]'s {{decc|EV7}} based in [[wikipedia:Marlboro, Massachusetts|Marlboro, Massachusetts]] under the lead of Cavium's CTO Richard Kessler (who was previously the chief architect of the {{decc|EV7}}). The fully custom final design proved to be around three to five times faster than the synthesized MIPS64 core.

== Codenames ==
{| class="wikitable"
! Family !! Description
|-
| {{cavium|Octeon}} ||  Enterprise network services processor (NSP)
|-
| {{cavium|Octeon Plus}} ||  Second generation (higher clock, bigger cache)
|}

== Process Technology ==
Chips were fabricated by [[TSMC]] on their [[0.13-micron]] [[CMOS]] process. By [[2007]] when Cavium released their {{cavium|OCTEON Plus}} family they've transitioned to TSMC's [[90 nm process]].

== Architecture ==
cnMIPS is the first implementation of the {{mips|MIPS64}} Release 2 ISA. Cavium's design goals were a target clock speed of around 600 MHz. Being primarily designed for network applications, the [[FPU]] was omitted as complex [[floating point]] operations are uncommon.

=== Interfaces ===
cnMIPS includes a number of additional interfaces:

* SPI-4.2 interface
* Gigabit Ethernet MAC ([[RGMII]]/[[GMII]])
* PLL
* 64-bit 66-133 MHz PCI/PCI-X host/slave controller
* USB 2.0
* TDM/PCM

There is no [[HyperTransport]] interface implemented. Also note the cnMIPS was planned to have a [[PCI Express]] interface but was eventually left out due to delays. Cavium did offer a number of bridge chips as a stopgap solution when desired.

With the introduction of the {{cavium|OCTEON Plus}} family, cavium introduced faster interfaces, including
* [[SGMII]]
* [[XAUI]]
* PCI Express x4, x8

=== Special Functional Units ===
Designed for network-heavy operations, cnMIPS implements an array of security and compression units.

* Compression/Decompression
** ZIP engine supporting fixed or dynamic [[Huffman code]] compression algorithms, [[GZIP]], [[PKZIP]] 
* Security
** [[DES]]
** [[Triple DES]] (3DES)
** [[AES]]
** [[Message Digest 5]] (MD5)
** [[Secure Hash Algorithm]] (SHA-1)
** [[Diffie-Hellman]]
** [[RSA]] & [[Rivest Cipher 4]] (RC4)
* Regular Expression Engine
* TCP accelerator
* QoS accelerator

=== Memory Hierarchy ===
* Cache
** L1I Cache:
*** 16-32 KiB 64-way set associative
*** per core
** L1D Cache:
*** 8-16 KiB 8-way set associative
*** Write-through policy
*** per core
** L2 Cache:
*** Up to 1 MiB 8-way set associative
*** 128 B line locking and partitioning
*** shared by all cores
* TLB
** 32-entry
* MMU
** 2 KiB write buffer

Note that the [[L2$]] is shared across all the cores over a coherent bus operating at the core's native clock frequency of 600 MHz for a theoretical bandwidth of 230 Gb/s. There is a 12-cycle latency between the L1 and L2 caches. The L2 is connected directly to an on-chip [[SDRAM]] controller with support for up to 16 GiB of single-channel 64-bit (and 128-bit for 8- and 16-core models) [[DDR1]]/[[DDR2]] up to 400 MHz for 5.96 GiB/s (6.4 GB/s) and 11.92 GiB/s (12.8 GB/s) for the 8- and 16- cores.

== All cnMIPS Chips ==
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<table class="wikitable sortable tc12 tc13 tc14 tc15 tc16 tc17">
<tr><th colspan="17" style="background:#D6D6FF;">All cnMIPS Microprocessors</th></tr>
<tr><th colspan="9">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</th></tr>
<tr><th>Model</th><th>Family</th><th>Price</th><th>Launched</th><th>Cores</th><th>L1$</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th><th>Encryption</th><th>Compression</th><th>RegEx</th><th>TCP</th><th>QoS</th></tr>
{{#ask: [[Category:microprocessor models by cavium]][[microarchitecture::cnMIPS]]
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 |?l1$ size#KiB
 |?l2$ size#KiB
 |?power dissipation
 |?base frequency
 |?supported memory type
 |?max memory
 |?has ecc memory support
 |?has hardware accelerators for cryptography
 |?has hardware accelerators for data compression
 |?has hardware accelerators for regular expression
 |?has hardware accelerators for tcp packet processing
 |?has hardware accelerators for network quality of service processing
 |format=template
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{{table count|col=17|ask=[[Category:microprocessor models by cavium]][[microarchitecture::cnMIPS]]}}
</table>
codename	cnMIPS +
core count	2 + and 4 +
designer	Cavium +
first launched	September 13, 2004 +
full page name	cavium/microarchitectures/cnmips +
instance of	microarchitecture +
instruction set architecture	MIPS64 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	cnMIPS +
pipeline stages	5 +
process	130 nm (0.13 μm, 1.3e-4 mm) +