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Latest revision | Your text | ||
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| phase-out = | | phase-out = | ||
| process = 130 nm | | process = 130 nm | ||
− | |||
| cores = 2 | | cores = 2 | ||
| cores 2 = 4 | | cores 2 = 4 | ||
− | | | + | | cores 3 = 8 |
− | | cores 4 | + | | cores 4 = 16 |
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| pipeline = Yes | | pipeline = Yes | ||
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| l1i per = core | | l1i per = core | ||
| l1i desc = 64-way set associative | | l1i desc = 64-way set associative | ||
− | | l1d = 8 | + | | l1d = 8 KiB |
| l1d per = core | | l1d per = core | ||
| l1d desc = 8-way set associative | | l1d desc = 8-way set associative | ||
− | | l2 = 1 | + | | l2 = 1 MiB |
| l2 per = chip | | l2 per = chip | ||
| l2 desc = 8-way set associative | | l2 desc = 8-way set associative | ||
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| l3 desc = | | l3 desc = | ||
− | | core names = Yes | + | | core names = <!-- Yes if specify --> |
− | | core name = | + | | core name = |
+ | | core name 2 = | ||
+ | | core name N = | ||
| succession = Yes | | succession = Yes | ||
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There is no [[HyperTransport]] interface implemented. Also note the cnMIPS was planned to have a [[PCI Express]] interface but was eventually left out due to delays. Cavium did offer a number of bridge chips as a stopgap solution when desired. | There is no [[HyperTransport]] interface implemented. Also note the cnMIPS was planned to have a [[PCI Express]] interface but was eventually left out due to delays. Cavium did offer a number of bridge chips as a stopgap solution when desired. | ||
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=== Special Functional Units === | === Special Functional Units === | ||
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*** per core | *** per core | ||
** L1D Cache: | ** L1D Cache: | ||
− | *** 8 | + | *** 8 KiB 8-way set associative |
*** Write-through policy | *** Write-through policy | ||
*** per core | *** per core |
Facts about "cnMIPS - Microarchitectures - Cavium"
codename | cnMIPS + |
core count | 2 + and 4 + |
designer | Cavium + |
first launched | September 13, 2004 + |
full page name | cavium/microarchitectures/cnmips + |
instance of | microarchitecture + |
instruction set architecture | MIPS64 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | cnMIPS + |
pipeline stages | 5 + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |