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== Overview == | == Overview == | ||
− | In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) | + | In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) TFLOPS. The efficiency of the chip slightly worsens at high-performance mode in favors of higher performances. In this mode the processor has a peak performance of 166.4 TOPS and 83.2 half-precision TFLOPS. |
<table class="wikitable"> | <table class="wikitable"> | ||
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<tr><th>Frequency</th><td>1 GHz</td><td>1.3 GHz</td></tr> | <tr><th>Frequency</th><td>1 GHz</td><td>1.3 GHz</td></tr> | ||
<tr><th>8-bit Int</th><td>128 TOPS</td><td>166.4 TOPS</td></tr> | <tr><th>8-bit Int</th><td>128 TOPS</td><td>166.4 TOPS</td></tr> | ||
− | <tr><th>16-bit FP</th><td>64 | + | <tr><th>16-bit FP</th><td>64 FLOPS</td><td>83.2 FLOPS</td></tr> |
</table> | </table> | ||
Facts about "MLU100 - Cambricon"
base frequency | 1,300 MHz (1.3 GHz, 1,300,000 kHz) + |
designer | Cambricon + |
family | MLU + |
first announced | November 7, 2017 + |
first launched | May 3, 2018 + |
full page name | cambricon/mlu/mlu100 + |
has ecc memory support | true + |
isa | MLUv100 + |
ldate | May 3, 2018 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Server + |
max memory bandwidth | 95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + |
max memory channels | 4 + |
model number | MLU100 + |
name | MLU100 + |
supported memory type | DDR4-3200 + |
tdp | 80 W (80,000 mW, 0.107 hp, 0.08 kW) + and 110 W (110,000 mW, 0.148 hp, 0.11 kW) + |
technology | CMOS + |