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== Overview ==
 
== Overview ==
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In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) [[TFLOPS]]. The efficiency of the chip slightly worsens at high-performance mode in favors of higher performances. In this mode the processor has a peak performance of 166.4 TOPS and 83.2 half-precision TFLOPS.
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In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) TFLOPS. The efficiency of the chip slightly worsens at high-performance mode in favors of higher performances. In this mode the processor has a peak performance of 166.4 TOPS and 83.2 half-precision TFLOPS.
  
 
<table class="wikitable">
 
<table class="wikitable">
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<tr><th>Frequency</th><td>1 GHz</td><td>1.3 GHz</td></tr>
 
<tr><th>Frequency</th><td>1 GHz</td><td>1.3 GHz</td></tr>
 
<tr><th>8-bit Int</th><td>128 TOPS</td><td>166.4 TOPS</td></tr>
 
<tr><th>8-bit Int</th><td>128 TOPS</td><td>166.4 TOPS</td></tr>
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<tr><th>16-bit FP</th><td>64 TFLOPS</td><td>83.2 TFLOPS</td></tr>
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<tr><th>16-bit FP</th><td>64 FLOPS</td><td>83.2 FLOPS</td></tr>
 
</table>
 
</table>
  

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Facts about "MLU100 - Cambricon"
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base frequency1,300 MHz (1.3 GHz, 1,300,000 kHz) +
designerCambricon +
familyMLU +
first announcedNovember 7, 2017 +
first launchedMay 3, 2018 +
full page namecambricon/mlu/mlu100 +
has ecc memory supporttrue +
isaMLUv100 +
ldateMay 3, 2018 +
main imageFile:cambricon mlu100 front.png +
manufacturerTSMC +
market segmentServer +
max memory bandwidth95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) +
max memory channels4 +
model numberMLU100 +
nameMLU100 +
supported memory typeDDR4-3200 +
tdp80 W (80,000 mW, 0.107 hp, 0.08 kW) + and 110 W (110,000 mW, 0.148 hp, 0.11 kW) +
technologyCMOS +