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Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the [[edge computing|edge]] to [[hyperscalers]] data centers. Departing from Arm's low-power {{armh|cortex|mobile cores}}, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior {{armh|Cosmos|l=arch}} platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance.
 
Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the [[edge computing|edge]] to [[hyperscalers]] data centers. Departing from Arm's low-power {{armh|cortex|mobile cores}}, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior {{armh|Cosmos|l=arch}} platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance.
  
The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage [[out-of-order]] core with private [[L1]] and [[L2]] caches. The core is intended to leverage Arm's {{armh|Coherent Mesh Network}} 600 (CMN-600) [[interconnect]] to scale from as little as a [[quad-core]] design to as much as [[128 cores]] and from a single [[DDR]] channel all the way up to eight channels, depending on the kind of workload being addressed. Extending the base design is a framework for [[multiprocessing]] support as well as [[chiplets]] support which can be used by companies who are looking to improve [[yield]] and manufacturability with large SoC designs. The N1 is also designed to work seamlessly with the {{\\|Neoverse E1}} which was introduced at the same time as N1 but is optimized for high throughput multithreaded workloads.
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The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage [[out-of-order]] core with private [[L1]] and [[L2]] caches. The core is intended to leverage Arm's {{armh|Coherent Mesh Network}} 600 (CMN-600) [[interconnect]] to scale from as little as a [[quad-core]] design to as much as [[128 cores]], depending on the kind of workload being addressed. The N1 is also designed to work seamlessly with the {{\\|Neoverse E1}} which was introduced at the same time as N1 but is optimized for high throughput multithreaded workloads.
  
 
== Core ==
 
== Core ==

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codenameNeoverse N1 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedFebruary 20, 2019 +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N1 +
pipeline stages11 +
process7 nm (0.007 μm, 7.0e-6 mm) +