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Latest revision | Your text | ||
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! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target | ! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target | ||
|- | |- | ||
− | | [[GCC]] || <code>-march=armv8 | + | | [[GCC]] || <code>-march=armv8-2a</code> || <code>-mtune=neoverse-n1</code> || <code>-mcpu=neoverse-n1</code> |
|- | |- | ||
− | | [[LLVM]] || <code>-march=armv8 | + | | [[LLVM]] || <code>-march=armv8-2a</code> || <code>-mtune=neoverse-n1</code> || <code>-mcpu=neoverse-n1</code> |
|} | |} | ||
Facts about "Neoverse N1 - Microarchitectures - ARM"
codename | Neoverse N1 + |
core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
designer | ARM Holdings + |
first launched | February 20, 2019 + |
full page name | arm holdings/microarchitectures/neoverse n1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Neoverse N1 + |
pipeline stages | 11 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |