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== History == | == History == | ||
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]] | [[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]] | ||
− | + | Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019. | |
== Release Dates == | == Release Dates == | ||
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== Process Technology == | == Process Technology == | ||
Ares specifically takes advantage of the power and area advantages of the [[7 nm process]]. | Ares specifically takes advantage of the power and area advantages of the [[7 nm process]]. | ||
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== Architecture == | == Architecture == | ||
The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload. | The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload. | ||
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* [[7 nm process]] | * [[7 nm process]] | ||
* Core | * Core | ||
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Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the [[edge computing|edge]] to [[hyperscalers]] data centers. Departing from Arm's low-power {{armh|cortex|mobile cores}}, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior {{armh|Cosmos|l=arch}} platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance. | Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the [[edge computing|edge]] to [[hyperscalers]] data centers. Departing from Arm's low-power {{armh|cortex|mobile cores}}, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior {{armh|Cosmos|l=arch}} platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance. | ||
− | The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage [[out-of-order]] core with private [[L1]] and [[L2]] caches. The core is intended to leverage Arm's {{armh|Coherent Mesh Network}} 600 (CMN-600) [[interconnect]] to scale from as little as a [[quad-core]] design to as much as [[128 cores]] | + | The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage [[out-of-order]] core with private [[L1]] and [[L2]] caches. The core is intended to leverage Arm's {{armh|Coherent Mesh Network}} 600 (CMN-600) [[interconnect]] to scale from as little as a [[quad-core]] design to as much as [[128 cores]], depending on the kind of workload being addressed. The N1 is also designed to work seamlessly with the {{\\|Neoverse E1}} which was introduced at the same time as N1 but is optimized for high throughput multithreaded workloads. |
== Core == | == Core == | ||
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* Drew Henry, direct communication | * Drew Henry, direct communication | ||
* Most of the technical details were obtained directly from Arm | * Most of the technical details were obtained directly from Arm | ||
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Facts about "Neoverse N1 - Microarchitectures - ARM"
codename | Neoverse N1 + |
core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
designer | ARM Holdings + |
first launched | February 20, 2019 + |
full page name | arm holdings/microarchitectures/neoverse n1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Neoverse N1 + |
pipeline stages | 11 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |