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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=Ares |
|designer=ARM Holdings | |designer=ARM Holdings | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
|introduction=February 20, 2019 | |introduction=February 20, 2019 | ||
|process=7 nm | |process=7 nm | ||
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|oooe=Yes | |oooe=Yes | ||
|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
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|predecessor=Cosmos | |predecessor=Cosmos | ||
|predecessor link=arm_holdings/cosmos | |predecessor link=arm_holdings/cosmos | ||
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== History == | == History == | ||
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]] | [[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]] | ||
− | + | Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019. | |
== Release Dates == | == Release Dates == | ||
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== Process Technology == | == Process Technology == | ||
Ares specifically takes advantage of the power and area advantages of the [[7 nm process]]. | Ares specifically takes advantage of the power and area advantages of the [[7 nm process]]. | ||
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== Architecture == | == Architecture == | ||
The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload. | The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload. | ||
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* [[7 nm process]] | * [[7 nm process]] | ||
* Core | * Core | ||
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== Overview == | == Overview == | ||
− | + | {{empty section}} | |
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== Core == | == Core == | ||
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== Die == | == Die == | ||
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* 1.2 mm² die size (1C + 512 KiB L2) | * 1.2 mm² die size (1C + 512 KiB L2) | ||
* 1.4 mm² die size (1C + 1 MiB L2) | * 1.4 mm² die size (1C + 1 MiB L2) | ||
− | * 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 | + | * 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 W (1.0 V) |
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* Drew Henry, direct communication | * Drew Henry, direct communication | ||
* Most of the technical details were obtained directly from Arm | * Most of the technical details were obtained directly from Arm | ||
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Facts about "Neoverse N1 - Microarchitectures - ARM"
codename | Neoverse N1 + |
core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
designer | ARM Holdings + |
first launched | February 20, 2019 + |
full page name | arm holdings/microarchitectures/neoverse n1 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Neoverse N1 + |
pipeline stages | 11 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |