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=== Convolutions optimizations === | === Convolutions optimizations === | ||
− | [[File:mlp compute engine overview.svg|thumb| | + | [[File:mlp compute engine overview.svg|thumb|300px|right|CEs]] |
Each CE comes with a slice of SRAM. The exact size is identical for all the CEs in the MLP and are configurable in size from 64 KiB to 256 KiB. Since the entire execution is statically scheduled, at compile-time, the compiler will partition the SRAM into a number of sections including the [[input feature map]] (IFM) such as the input activations, the model weights in compressed form, and the [[output feature maps]] for the output activations. | Each CE comes with a slice of SRAM. The exact size is identical for all the CEs in the MLP and are configurable in size from 64 KiB to 256 KiB. Since the entire execution is statically scheduled, at compile-time, the compiler will partition the SRAM into a number of sections including the [[input feature map]] (IFM) such as the input activations, the model weights in compressed form, and the [[output feature maps]] for the output activations. | ||
codename | MLP + |
designer | Arm Holdings + |
first launched | 2018 + |
full page name | arm holdings/microarchitectures/mlp + |
instance of | microarchitecture + |
manufacturer | TSMC +, Samsung + and UMC + |
name | MLP + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |
processing element count | 4 +, 12 +, 8 + and 16 + |