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|decode=2-way | |decode=2-way | ||
|isa=ARMv7 | |isa=ARMv7 | ||
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|predecessor=ARM11 | |predecessor=ARM11 | ||
|predecessor link=arm_holdings/microarchitectures/arm11 | |predecessor link=arm_holdings/microarchitectures/arm11 | ||
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}} | }} | ||
'''Cortex-A8''' (codename '''Tiger''') is the successor to the {{armh|ARM11|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center. | '''Cortex-A8''' (codename '''Tiger''') is the successor to the {{armh|ARM11|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center. | ||
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== Architecture == | == Architecture == | ||
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* [[ARMv7]] (from [[ARMv6]]) | * [[ARMv7]] (from [[ARMv6]]) | ||
** Support for {{arm|NEON}} (ASIMD) | ** Support for {{arm|NEON}} (ASIMD) | ||
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** {{arm|TrustZone}} | ** {{arm|TrustZone}} | ||
** {{arm|Thumb-2}} | ** {{arm|Thumb-2}} | ||
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=== Block Diagram === | === Block Diagram === | ||
− | + | {{empty section}} | |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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** L1I Cache | ** L1I Cache | ||
*** 16 KiB OR 32 KiB (configurable) | *** 16 KiB OR 32 KiB (configurable) | ||
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** L1D Cache | ** L1D Cache | ||
*** 16 KiB OR 32 KiB (configurable) | *** 16 KiB OR 32 KiB (configurable) | ||
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** L2 Cache | ** L2 Cache | ||
*** 0 KiB OR 128 KiB OR 1 MiB (configurable) | *** 0 KiB OR 128 KiB OR 1 MiB (configurable) | ||
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*** Optional Parity and ECC | *** Optional Parity and ECC | ||
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== Die == | == Die == | ||
− | * [[65 nm process]] | + | * [[65 nm process]] |
− | * Up to | + | * Up to 1 GHz |
− | * 4 mm² ( | + | * 4 mm² (core only, no NEON, L2 cache, and embedded trace) |
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* <= 300 mW | * <= 300 mW | ||
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Facts about "Cortex-A8 - Microarchitectures - ARM"
codename | Cortex-A8 + |
designer | ARM Holdings + |
first launched | October 5, 2005 + |
full page name | arm holdings/microarchitectures/cortex-a8 + |
instance of | microarchitecture + |
instruction set architecture | ARMv7 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A8 + |
pipeline stages | 13 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) + |