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== Performance claims == | == Performance claims == | ||
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=== DSU Cluster === | === DSU Cluster === | ||
− | The Cortex-A78 is designed to be integrated into a [[DynamIQ Shared Unit]] (DSU) cluster with up to [[eight cores]]. Up to four Cortex-A78s may be clustered together. The cluster may also inclde up to four additional [[little cores]] such as the {{\\|Cortex-A55}} in a [[big.LITTLE]] configuration. Additionally, one or more of the A78 cores [[arm_holdings/microarchitectures/cortex-x1#DSU Cluster|may be swapped out]] for a {{\\|Cortex-X1}} core in order to achieve even higher performance. Compared to a quad-core {{\\|Cortex-A77|A77}} cluster on [[N7|7 nm]], a quad-core A78 cluster on [[N5|5 nm]] provides +20% sustained performance improvement while reducing the silicon area by about 15%. | + | The Cortex-A78 is designed to be integrated into a [[DynamIQ Shared Unit]] (DSU) cluster with up to [[eight cores]]. Up to four Cortex-A78s may be clustered together. The cluster may also inclde up to four additional [[little cores]] such as the {{\\|Cortex-A55}} in a [[big.LITTLE]] configuration. Additionally, one or more of the A78 cores [[arm_holdings/microarchitectures/cortex-x1#DSU Cluster|may be swapped out]] for a {{\\|Cortex-X1}} core in order to achieve even higher performance. Compared to a quad-core {{\\|Cortex-A77|A77}} cluster on [[N7|7 nm]], a quad-core {{\\|Cortex-A78|A78}} cluster on [[N5|5 nm]] provides +20% sustained performance improvement while reducing the silicon area by about 15%. |
== Core == | == Core == | ||
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===== Memory subsystem ===== | ===== Memory subsystem ===== | ||
− | The memory subsystem was improved on the A78. Whereas the {{\\|A77}} had two generic [[address-generation unit]] - each capable of supporting both loads and stores, Hercules adds a new | + | The memory subsystem was improved on the A78. Whereas the {{\\|A77}} had two generic [[address-generation unit]] - each capable of supporting both loads and stores, Hercules adds a new deducted load AGU unit, including the load bandwidth by 50%. In other words, the Cortex-A78 is capable of performing either a loads or a store on 2 ports (any combination, e.g., LD+ST or ST+ST) and another load on a third port. Along with those changes, Arm doubled the store-data bandwidth from 16B/cycle to 32B/cycle. |
Like the instruction cache, the [[level 1 data cache]] on Hercules was also made configurable, allowing for either 32 KiB or 64 KiB and with an optional ECC protection per 32 bits. It is [[virtually indexed, physically tagged]] which behaves as a [[physically indexed, physically tagged]] 4-way set-associative cache. The L1D cache implements a [[pseudo-LRU]] [[cache replacement]] policy. It features a 4-cycle fastest load-to-use latency with two read ports and one write port meaning it can do two 16B loads/cycle and one 32B store/cycle. From the L1, the A78 supported up to 20 outstanding non-prefetch misses. Previously, the {{\\|A77}} had an 85-entry load buffer and a 90-entry store buffer. Arm says the functionality of those two buffers is now distributed across several structures. Hercules improved the data prefetchers. Arm says Hercules introduced a number of new prefetch engines, covering some new stride patterns and new irregular access patterns. | Like the instruction cache, the [[level 1 data cache]] on Hercules was also made configurable, allowing for either 32 KiB or 64 KiB and with an optional ECC protection per 32 bits. It is [[virtually indexed, physically tagged]] which behaves as a [[physically indexed, physically tagged]] 4-way set-associative cache. The L1D cache implements a [[pseudo-LRU]] [[cache replacement]] policy. It features a 4-cycle fastest load-to-use latency with two read ports and one write port meaning it can do two 16B loads/cycle and one 32B store/cycle. From the L1, the A78 supported up to 20 outstanding non-prefetch misses. Previously, the {{\\|A77}} had an 85-entry load buffer and a 90-entry store buffer. Arm says the functionality of those two buffers is now distributed across several structures. Hercules improved the data prefetchers. Arm says Hercules introduced a number of new prefetch engines, covering some new stride patterns and new irregular access patterns. |
Facts about "Cortex-A78 - Microarchitectures - ARM"
codename | Cortex-A78 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 26, 2020 + |
full page name | arm holdings/microarchitectures/cortex-a78 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A78 + |
pipeline stages | 13 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |