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=== DSU Cluster === | === DSU Cluster === | ||
− | The Cortex-A78 is designed to be integrated into a [[DynamIQ Shared Unit]] (DSU) cluster with up to [[eight cores]]. Up to four Cortex-A78s may be clustered together. The cluster may also inclde up to four additional [[little cores]] such as the {{\\|Cortex-A55}} in a [[big.LITTLE]] configuration. Additionally, one or more of the A78 cores [[arm_holdings/microarchitectures/cortex-x1#DSU Cluster|may be swapped out]] for a {{\\|Cortex-X1}} core in order to achieve even higher performance. Compared to a quad-core {{\\|Cortex-A77|A77}} cluster on [[N7|7 nm]], a quad-core A78 cluster on [[N5|5 nm]] provides +20% sustained performance improvement while reducing the silicon area by about 15%. | + | The Cortex-A78 is designed to be integrated into a [[DynamIQ Shared Unit]] (DSU) cluster with up to [[eight cores]]. Up to four Cortex-A78s may be clustered together. The cluster may also inclde up to four additional [[little cores]] such as the {{\\|Cortex-A55}} in a [[big.LITTLE]] configuration. Additionally, one or more of the A78 cores [[arm_holdings/microarchitectures/cortex-x1#DSU Cluster|may be swapped out]] for a {{\\|Cortex-X1}} core in order to achieve even higher performance. Compared to a quad-core {{\\|Cortex-A77|A77}} cluster on [[N7|7 nm]], a quad-core {{\\|Cortex-A78|A78}} cluster on [[N5|5 nm]] provides +20% sustained performance improvement while reducing the silicon area by about 15%. |
== Core == | == Core == |
Facts about "Cortex-A78 - Microarchitectures - ARM"
codename | Cortex-A78 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 26, 2020 + |
full page name | arm holdings/microarchitectures/cortex-a78 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A78 + |
pipeline stages | 13 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |