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− | + | {{headerbar|1|Block Diagram|icon=fa-drafting-compass}} | |
− | = | + | <h4 style="text-align: center;">Typical SoC</h4> |
− | :[[File:cortex-a77 soc block diagram.svg| | + | :[[File:cortex-a77 soc block diagram.svg|center|650px]] |
− | + | <h4 style="text-align: center;">Individual Core</h4> | |
− | + | :[[File:cortex-a77 block diagram.svg|center|950px]] | |
− | :[[File:cortex-a77 block diagram.svg| | + | {{headerbar|end}} |
=== Memory Hierarchy === | === Memory Hierarchy === |
Facts about "Cortex-A77 - Microarchitectures - ARM"
codename | Cortex-A77 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 27, 2019 + |
full page name | arm holdings/microarchitectures/cortex-a77 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC +, samsung + and SMIC + |
microarchitecture type | CPU + |
name | Cortex-A77 + |
pipeline stages | 13 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |