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|designer=ARM Holdings | |designer=ARM Holdings | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
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|introduction=May 27, 2019 | |introduction=May 27, 2019 | ||
|process=10 nm | |process=10 nm | ||
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|predecessor=Cortex-A76 | |predecessor=Cortex-A76 | ||
|predecessor link=arm holdings/microarchitectures/cortex-a76 | |predecessor link=arm holdings/microarchitectures/cortex-a76 | ||
− | |successor= | + | |successor=Hercules |
− | |successor link=arm holdings/microarchitectures/ | + | |successor link=arm holdings/microarchitectures/hercules |
}} | }} | ||
'''Cortex-A77''' (codename '''Deimos''') is the successor to the {{armh|Cortex-A76|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. Deimos was designed by Arm's Austin, Texas team. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A77, which implemented the {{arm|ARMv8.2}} ISA, is a high performance core which is often combined with a number of low(er) power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance. | '''Cortex-A77''' (codename '''Deimos''') is the successor to the {{armh|Cortex-A76|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. Deimos was designed by Arm's Austin, Texas team. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A77, which implemented the {{arm|ARMv8.2}} ISA, is a high performance core which is often combined with a number of low(er) power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance. | ||
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== Architecture == | == Architecture == | ||
=== Key changes from {{\\|Cortex-A76}} === | === Key changes from {{\\|Cortex-A76}} === | ||
− | * | + | * Significant [[IPC]] uplift ([[Arm]] self-reported around 20% IPC on [[SPEC CPU2006]]/[[SPEC CPU2017]] int) |
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* Front-end | * Front-end | ||
** [[Branch-prediction]] | ** [[Branch-prediction]] | ||
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*** 2x larger runahead window (64B, up from 32B) | *** 2x larger runahead window (64B, up from 32B) | ||
*** 1.33x larger BTB capacity (8K-entry, up from 6K) | *** 1.33x larger BTB capacity (8K-entry, up from 6K) | ||
− | *** 4x larger L1 | + | *** 4x larger L1 BRB capacity (64-entry, up from 16) |
** Improved prefetcher | ** Improved prefetcher | ||
** New [[L0]] MOP cache | ** New [[L0]] MOP cache |
Facts about "Cortex-A77 - Microarchitectures - ARM"
codename | Cortex-A77 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 27, 2019 + |
full page name | arm holdings/microarchitectures/cortex-a77 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC +, samsung + and SMIC + |
microarchitecture type | CPU + |
name | Cortex-A77 + |
pipeline stages | 13 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |