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*** 2x larger runahead window (64B, up from 32B) | *** 2x larger runahead window (64B, up from 32B) | ||
*** 1.33x larger BTB capacity (8K-entry, up from 6K) | *** 1.33x larger BTB capacity (8K-entry, up from 6K) | ||
− | *** 4x larger L1 | + | *** 4x larger L1 BRB capacity (64-entry, up from 16) |
** Improved prefetcher | ** Improved prefetcher | ||
** New [[L0]] MOP cache | ** New [[L0]] MOP cache |
Facts about "Cortex-A77 - Microarchitectures - ARM"
codename | Cortex-A77 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 27, 2019 + |
full page name | arm holdings/microarchitectures/cortex-a77 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC +, samsung + and SMIC + |
microarchitecture type | CPU + |
name | Cortex-A77 + |
pipeline stages | 13 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |