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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=CPH1911 |
|designer=ARM Holdings | |designer=ARM Holdings | ||
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|introduction=May 29, 2017 | |introduction=May 29, 2017 | ||
|process=16 nm | |process=16 nm | ||
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|cores 3=3 | |cores 3=3 | ||
|cores 4=4 | |cores 4=4 | ||
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|type=In-order | |type=In-order | ||
− | |oooe= | + | |oooe=Yes |
|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
|stages=8 | |stages=8 | ||
− | |decode= | + | |decode=1-way |
|isa=ARMv8.2 | |isa=ARMv8.2 | ||
|feature=Hardware virtualization | |feature=Hardware virtualization | ||
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|predecessor=Cortex-A53 | |predecessor=Cortex-A53 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a53 | |predecessor link=arm_holdings/microarchitectures/cortex-a53 | ||
− | |successor= | + | |successor=Helios |
− | |successor link=arm_holdings/microarchitectures/ | + | |successor link=arm_holdings/microarchitectures/helios |
}} | }} | ||
'''Cortex-A55''' (codename '''Ananke''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8.2}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A75|l=arch}}) in {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance. | '''Cortex-A55''' (codename '''Ananke''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8.2}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A75|l=arch}}) in {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance. | ||
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* [[Huawei]] | * [[Huawei]] | ||
* [[Unisoc]] | * [[Unisoc]] | ||
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}} | }} | ||
Facts about "Cortex-A55 - Microarchitectures - ARM"
codename | Cortex-A55 + |
core count | 1 +, 2 +, 3 + and 4 + |
designer | ARM Holdings + |
first launched | May 29, 2017 + |
full page name | arm holdings/microarchitectures/cortex-a55 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC +, Samsung +, GlobalFoundries + and SMIC + |
microarchitecture type | CPU + |
name | Cortex-A55 + |
pipeline stages | 8 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) + |