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ARM6's pipeline is identical to the ARM2. | ARM6's pipeline is identical to the ARM2. | ||
− | + | ==== Backward Compatibility ==== | |
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Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem by offering a compatibility mode. Two of the new control register bits are <code>prog32</code> and <code>data32</code> which can be set to change how the core behaves: | Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem by offering a compatibility mode. Two of the new control register bits are <code>prog32</code> and <code>data32</code> which can be set to change how the core behaves: | ||
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It's worth pointing out that when in 26-bit program space, only the four original modes (User, FIQ, IRQ, and Supervisor) are available and they behave in the same way as previous architectures in order to allow older programs to execute correctly. | It's worth pointing out that when in 26-bit program space, only the four original modes (User, FIQ, IRQ, and Supervisor) are available and they behave in the same way as previous architectures in order to allow older programs to execute correctly. | ||
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=== Cache === | === Cache === |
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |