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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=ARM6 |
|designer=ARM Holdings | |designer=ARM Holdings | ||
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|manufacturer=VLSI Technology | |manufacturer=VLSI Technology | ||
|manufacturer 2=GEC-Plessey Semiconductors | |manufacturer 2=GEC-Plessey Semiconductors | ||
|manufacturer 3=Sharp | |manufacturer 3=Sharp | ||
− | | | + | |introduction=1993 |
|process=0.8 µm | |process=0.8 µm | ||
|cores=1 | |cores=1 | ||
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|type=Scalar | |type=Scalar | ||
|type 2=Pipelined | |type 2=Pipelined | ||
|stages=3 | |stages=3 | ||
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|decode=1-way | |decode=1-way | ||
|isa=ARMv3 | |isa=ARMv3 | ||
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|l1=4 KiB | |l1=4 KiB | ||
|l1 per=core | |l1 per=core | ||
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|predecessor=ARM3 | |predecessor=ARM3 | ||
|predecessor link=acorn/microarchitectures/arm3 | |predecessor link=acorn/microarchitectures/arm3 | ||
− | |successor= | + | |successor=ARM7 |
− | |successor link=arm holdings/microarchitectures/ | + | |successor link=arm holdings/microarchitectures/arm7 |
}} | }} | ||
− | '''ARM6''' is an [[ARM]] microarchitecture designed by [[ARM Holdings]] and introduced in | + | '''ARM6''' is an [[ARM]] microarchitecture designed by [[ARM Holdings]] and introduced in 1993 as a successor to the {{acorn|ARM3|l=arch}}. This was the first design by ARM as an independent company after being spun-off from [[Acorn Computers]]. |
== History == | == History == | ||
{{see also|arm/history|l1=ARM's History}} | {{see also|arm/history|l1=ARM's History}} | ||
− | Following ARM's incorporation in November 1990 after being spun-off from [[Acorn Computers]], ARM continued to develop the ARM microprocessor. In | + | Following ARM's incorporation in November 1990 after being spun-off from [[Acorn Computers]], ARM continued to develop the ARM microprocessor. In 1993 ARM introduced the ARM6 MacroCell, a substantial improvement over the previous {{acorn|ARM3|l=arch}} microarchitecture. The same year ARM signed with a number of additional licensees beyond [[VLSI Technology]], including [[Sharp]] and [[GEC-Plessey]]. |
The popularity of the ARM6 can be largely attributed to [[Apple]]'s adaptation of the processor in their {{apple|Newton}} PDAs. | The popularity of the ARM6 can be largely attributed to [[Apple]]'s adaptation of the processor in their {{apple|Newton}} PDAs. | ||
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=== Key changes from {{\\|ARM3}} === | === Key changes from {{\\|ARM3}} === | ||
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* 32-bit address space (from {{arm|26-bit}}) | * 32-bit address space (from {{arm|26-bit}}) | ||
** Can map 4 GiB of memory | ** Can map 4 GiB of memory | ||
** {{arm|CPSR}} & {{arm|SPSR}} moved out of the [[program counter]] | ** {{arm|CPSR}} & {{arm|SPSR}} moved out of the [[program counter]] | ||
** Their own separate registers | ** Their own separate registers | ||
− | + | * New Modes | |
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− | * New Modes | ||
** Abort (abt) | ** Abort (abt) | ||
** Undefined (und) | ** Undefined (und) | ||
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The ARM6 is a further evolutionary enhancement of the {{acorn|ARM3|l=arch}}. The new chip integrated a number of highly desired features - particularly ones needed by [[Apple]]. The ARM6, departs from all the {{arm|history|previous ARM chips}} by featuring a full 32-bit address and data buses. To {{arm|26-bit|facilitate}} the larger address space, ARM (previously [[Acorn]]) had to move the status flags from the program counter to its own {{arm|CPSR|independent register}}. In total, the ARM6 has 37 registers consisting of 31 {{arch|32}} general-purpose registers and 6 additional status registers. | The ARM6 is a further evolutionary enhancement of the {{acorn|ARM3|l=arch}}. The new chip integrated a number of highly desired features - particularly ones needed by [[Apple]]. The ARM6, departs from all the {{arm|history|previous ARM chips}} by featuring a full 32-bit address and data buses. To {{arm|26-bit|facilitate}} the larger address space, ARM (previously [[Acorn]]) had to move the status flags from the program counter to its own {{arm|CPSR|independent register}}. In total, the ARM6 has 37 registers consisting of 31 {{arch|32}} general-purpose registers and 6 additional status registers. | ||
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==== Pipeline ==== | ==== Pipeline ==== | ||
{{main|acorn/microarchitectures/arm2#Pipeline|l1=ARM2 Pipeline}} | {{main|acorn/microarchitectures/arm2#Pipeline|l1=ARM2 Pipeline}} | ||
ARM6's pipeline is identical to the ARM2. | ARM6's pipeline is identical to the ARM2. | ||
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=== Cache === | === Cache === |
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |