From WikiChip
Editing arm holdings/microarchitectures/arm6
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 2: | Line 2: | ||
{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=ARM6 |
|designer=ARM Holdings | |designer=ARM Holdings | ||
− | |||
− | |||
− | |||
|manufacturer=VLSI Technology | |manufacturer=VLSI Technology | ||
|manufacturer 2=GEC-Plessey Semiconductors | |manufacturer 2=GEC-Plessey Semiconductors | ||
|manufacturer 3=Sharp | |manufacturer 3=Sharp | ||
− | | | + | |introduction=1993 |
|process=0.8 µm | |process=0.8 µm | ||
|cores=1 | |cores=1 | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|type=Scalar | |type=Scalar | ||
|type 2=Pipelined | |type 2=Pipelined | ||
|stages=3 | |stages=3 | ||
− | |||
− | |||
|decode=1-way | |decode=1-way | ||
|isa=ARMv3 | |isa=ARMv3 | ||
− | |||
− | |||
− | |||
|l1=4 KiB | |l1=4 KiB | ||
|l1 per=core | |l1 per=core | ||
Line 35: | Line 20: | ||
|predecessor=ARM3 | |predecessor=ARM3 | ||
|predecessor link=acorn/microarchitectures/arm3 | |predecessor link=acorn/microarchitectures/arm3 | ||
− | |successor= | + | |successor=ARM7 |
− | |successor link=arm holdings/microarchitectures/ | + | |successor link=arm holdings/microarchitectures/arm7 |
}} | }} | ||
− | '''ARM6''' is an [[ARM]] microarchitecture designed by [[ARM Holdings]] and introduced in | + | '''ARM6''' is an [[ARM]] microarchitecture designed by [[ARM Holdings]] and introduced in 1993 as a successor to the {{acorn|ARM3|l=arch}}. This was the first design by ARM as an independent company after being spun-off from [[Acorn Computers]]. |
== History == | == History == | ||
{{see also|arm/history|l1=ARM's History}} | {{see also|arm/history|l1=ARM's History}} | ||
− | Following ARM's incorporation in November 1990 after being spun-off from [[Acorn Computers]], ARM continued to develop the ARM microprocessor. In | + | Following ARM's incorporation in November 1990 after being spun-off from [[Acorn Computers]], ARM continued to develop the ARM microprocessor. In 1993 ARM introduced the ARM6 MacroCell, a substantial improvement over the previous {{acorn|ARM3|l=arch}} microarchitecture. The same year ARM signed with a number of additional licensees beyond [[VLSI Technology]], including [[Sharp]] and [[GEC-Plessey]]. |
The popularity of the ARM6 can be largely attributed to [[Apple]]'s adaptation of the processor in their {{apple|Newton}} PDAs. | The popularity of the ARM6 can be largely attributed to [[Apple]]'s adaptation of the processor in their {{apple|Newton}} PDAs. | ||
Line 54: | Line 39: | ||
=== Key changes from {{\\|ARM3}} === | === Key changes from {{\\|ARM3}} === | ||
− | |||
− | |||
* 32-bit address space (from {{arm|26-bit}}) | * 32-bit address space (from {{arm|26-bit}}) | ||
** Can map 4 GiB of memory | ** Can map 4 GiB of memory | ||
Line 61: | Line 44: | ||
** Their own separate registers | ** Their own separate registers | ||
** Backwards compatibility mode | ** Backwards compatibility mode | ||
− | + | * New Modes | |
− | * New Modes | ||
** Abort (abt) | ** Abort (abt) | ||
** Undefined (und) | ** Undefined (und) | ||
Line 111: | Line 93: | ||
ARM6's pipeline is identical to the ARM2. | ARM6's pipeline is identical to the ARM2. | ||
− | + | ==== Backward Compatibility ==== | |
− | |||
− | |||
− | |||
Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem by offering a compatibility mode. Two of the new control register bits are <code>prog32</code> and <code>data32</code> which can be set to change how the core behaves: | Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem by offering a compatibility mode. Two of the new control register bits are <code>prog32</code> and <code>data32</code> which can be set to change how the core behaves: | ||
Line 129: | Line 108: | ||
|} | |} | ||
− | It's | + | It's wroth pointing out that when in 26-bit program space, only the four original modes (User, FIQ, IRQ, and Supervisor) are available and they behave in the same way as previous architectures in order to allow older programs to execute correctly. |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Cache === | === Cache === |
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |