Editing arm holdings/microarchitectures/arm250

{{armh title|ARM250|arch}}
{{microarchitecture
|atype=CPU
|name=ARM250
|designer=ARM Holdings
|manufacturer=VLSI Technology
|introduction=1992
|process=1 µm
|cores=1
|type=Scalar
|type 2=Pipelined
|stages=3
|decode=1-way
|isa=ARMv2a
|core name=ARM250
|predecessor=ARM3
|predecessor link=acorn/microarchitectures/arm3
}}
'''ARM250''' was a [[system on a chip]] microarchitecture that was introduced by [[ARM Holdings]] around the same time the {{\\|ARM6}} was introduced.

== Overview ==

== Architecture ==
=== Block Diagram ===
==== Entire Chip ====
: [[File:arm250 block diagram.svg|600px]]

==== Core ====
: [[File:arm2 block diagram.svg|650px]]

== Die ==

== Documents ==
* [[:File:arm250 ds.pdf|ARM250 Datasheet]], August 11, 1992
@@ Line 19: / Line 19: @@
 '''ARM250''' was a [[system on a chip]] microarchitecture that was introduced by [[ARM Holdings]] around the same time the {{\\|ARM6}} was introduced.
-== History ==
+== Overview ==
-{{see also|arm/history|l1=ARM's History}}
-With the development of the {{\\|ARM6}} and a [[process shrink]] by [[vti|VTI]], ARM took the opportunity to introduce the ARM250. The ARM250 is a very high integration chip - incorporating the {{acorn|ARM3|l=arch}} core along with most of the new MMU logic that was developed for the {{\\|ARM6}} along with all the support chips that were previously needed for the ARM3/2 - the MEMC chip (Memory Controller), VIDC chip (Video Controller), IOC/IOEB (I/O Controller).
-Note that the added L1 cache found on the {{acorn|ARM3|l=arch}} is not found on the ARM250.
-== Process Technology ==
-{{see also|1 µm process}}
-The ARM250 was implemented on a [[1 µm]] double-level metal (DLM) [[CMOS]] process.
 == Architecture ==
-The ARM250 doesn't introduce anything new in itself. The core is an {{acorn|ARM3|l=arch}} with the MMU logic taken from the {{\\|ARM6}} which was also released around the same time.
-=== Key changes from {{\\|ARM3}} ===
-* Integrates support chips on-die
-** Integrated MEMC
-** Integrated VIDC
-** Integrated IOEB/IOC
-* Virtual memory
-** Integrated [[MMU]] ({{\\|ARM6}}'s)
 === Block Diagram ===
 ==== Entire Chip ====
-: [[File:arm250 block diagram.svg|650px]]
+: [[File:arm250 block diagram.svg|600px]]
 ==== Core ====
-:''({{acorn|ARM3|l=arch}} core)''
 : [[File:arm2 block diagram.svg|650px]]
 == Die ==
-* [[1-micron process]] CMOS
-* 2 metal layers
-* 58 mm² die size
-* 98,019 transistors
-* $25 (for 100K quantities)
-* PJQFP-160
-== References ==
-* Muller, Mike. "ARM6: a high performance low power consumption macrocell." Compcon Spring'93, Digest of Papers.. IEEE, 1993.
 == Documents ==
 * [[:File:arm250 ds.pdf|ARM250 Datasheet]], August 11, 1992
codename	ARM250 +
core count	1 +
designer	ARM Holdings +
first launched	1992 +
full page name	arm holdings/microarchitectures/arm250 +
instance of	microarchitecture +
instruction set architecture	ARMv2a +
manufacturer	VLSI Technology +
microarchitecture type	CPU +
name	ARM250 +
pipeline stages	3 +
process	1,000 nm (1 μm, 0.001 mm) +