Editing apm/x-gene

{{apm title|X-Gene}}
{{ic family
| title             = X-Gene
| image             = x-gene_front.jpg
| caption           = 
| no image          = 
| developer         = AppliedMicro
| manufacturer      = TSMC
| type              = Microprocessors
| first announced   = October 28, 2011
| first launched    = 2012
| isa               = ARM
| microarch         = Storm
| microarch 2       = Shadowcat
| microarch 3       = Skylark
| word              = 64 bit
| proc              = 40 nm
| proc 2            = 28 nm
| proc 3            = 16 nm
| tech              = CMOS
| clock min         = 2.4 GHz
| clock max         = 3.3 GHz
| package           = 
| package 2         = 
| package 3         = 

| succession       = Yes
| predecessor      = 
| predecessor link = 
| successor        = eMAG
| successor link   = ampere computing/emag
}}
'''X-Gene''' was a family of {{arch|64}} [[ARM]] server microprocessors designed and introduced by [[AppliedMicro]].

== Overview ==
X-Gene was a family of high-performance multi-core ARM microprocessors first announced by [[AppliedMicro]] in 2011. Unlike their traditional product offering, X-Gene directly targeted high-performance data center servers, a market predominantly dominated by [[Intel]] {{intel|Xeon}} processors. AppliedMicro introduced two generations of server processors based on their own custom [[ARM]] microarchitectures - {{apm|Storm|l=arch}} and {{apm|Shadowcat|l=arch}}. Those two generations shipped a total of 25,000 units. In late [[2016]], [[MACOM]] acquired AppliedMicro resulting in the shelving of third-generation X-Gene based on the {{apm|Skylark|l=arch}} microarchitecture. The X-Gene [[intellectual property]] including most of the design team was eventually sold to [[Ampere Computing]] has rebranded the design and improved on it under the {{ampere|eMAG}} brand.

=== Naming Scheme ===
:[[File:appliedmicro x-gene naming.svg|550px]]

== Members ==
=== X-Gene 1 ===
{{see also|apm/microarchitectures/storm|l1=Storm microarchitecture}}
First-generation of X-Gene processors were announced in October 2011 and later launched in late 2012. X-Gene 1 processors are based on the {{apm|Storm|l=arch}} microarchitecture and were fabricated on [[TSMC]]'s [[40 nm process]]. Those processors had up to four memory channels and up to [[eight cores]] operating at up to 2.4 GHz.

* '''Mem:''' up to 4 memory channels, DDR3 @ up to 1866 MT/s
* '''Tech:''' [[ARMv8]] (ARMv8.0-A)
* '''I/O:''' 17 PCIe, SATA/SGMII, 2x SGMII/XFI, 1x RGMII

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           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc2 tc3 tc7">
{{comp table header|main|6:List of Storm-based Processors}}
{{comp table header|main|4:Processor|2:Memory}}
{{comp table header|cols|Launched|Cores|%Turbo|L3$|Type|Chans}}
{{#ask: [[Category:microprocessor models by appliedmicro]] [[microarchitecture::Storm]]
 |?full page name
 |?model number
 |?first launched
 |?core count
 |?turbo frequency#GHz
 |?l3$ size
 |?supported memory type
 |?max memory channels
 |format=template
 |template=proc table 3
 |userparam=8
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by appliedmicro]] [[microarchitecture::Storm]]}}
</table>
{{comp table end}}

=== X-Gene 2 ===
{{empty section}}

=== X-Gene 3 ===
{{empty section}}

== See also ==
* Cavium {{cavium|ThunderX2}}
* Qualcomm {{qualcomm|Centriq}}

== Bibliography ==
* David Schor. (February 5, 2018). "''[https://fuse.wikichip.org/news/776/x-gene-3-gets-a-second-chance-at-ampere-with-a-new-32-core-16nm-arm-processor/ X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor]''".
designer	AppliedMicro +
first announced	October 28, 2011 +
first launched	2012 +
full page name	apm/x-gene +
instance of	microprocessor family +
instruction set architecture	ARM +
main designer	AppliedMicro +
manufacturer	TSMC +
microarchitecture	Storm +, Shadowcat + and Skylark +
name	X-Gene +
process	40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +