Editing apm/x-gene/apm883208-x2

{{apm title|X-Gene 2 APM883208-X2}}
{{chip
|name=APM883208-X2
|no image=Yes
|designer=AppliedMicro
|manufacturer=TSMC
|model number=APM883208-X2
|market=Server
|first announced=September, 2014
|first launched=March, 2015
|family=X-Gene
|series=X-Gene 2
|turbo frequency=2,400 MHz
|isa=ARMv8
|isa family=ARM
|microarch=Shadowcat
|process=28 nm
|technology=CMOS
|word size=64 bit
|core count=8
|thread count=8
|max memory=256 GiB
|v core=0.9 V
|v io=1.8 V
|v io 2=2.5 V
|v io 3=3.3 V
|tdp=35 W
|tjunc min=0 °C
|tjunc max=90 °C
|predecessor=APM883208-X1
|predecessor link=apm/x-gene/apm883208-x1
}}
'''APM883208-X2''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2014]]. Fabricated on [[TSMC]] [[28 nm process]] based on the {{apm|Shadowcat|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.

== Cache ==
{{main|apm/microarchitectures/shadowcat#Memory_Hierarchy|l1=Shadowcat § Cache}}
{{cache size
|l1 cache=256 KiB
|l1i cache=128 KiB
|l1i break=4x32 KiB
|l1i desc=8-way set associative
|l1d cache=128 KiB
|l1d break=4x32 KiB
|l1d desc=8-way set associative
|l1d policy=Write-through with write-combine
|l2 cache=512 KiB
|l2 break=2x256 KiB
|l3 cache=4 MiB
|l3 break=1x4 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR3-1866
|ecc=Yes
|max mem=256 GiB
|controllers=1
|channels=2
|max bandwidth=27.82 GiB/s
|bandwidth schan=13.91 GiB/s
|bandwidth dchan=27.82 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=17
|pcie config=1x16+x1
|pcie config 2=2x8+x1
}}
{{expansions entry
|type=USB
|usb revision=2.0
|usb ports=2
}}
{{expansions entry
|type=SATA
|sata revision=3.0
|sata ports=6
}}
}}
* 2x I2C
* 4x UARTs
* GPIOs
* 2x SPI
* 2x SDIO 3.0
* JTAG / Trace

=== Network ===
{{network
|mii opts=Yes
|rgmii=Yes
|rgmii ports=4
|sgmii=Yes
|sgmii ports=1
}}

* Note: some ports are muxed

== Block diagram ==
:[[File:208-x2 block.png|800px]]

== Documents ==
* [[:File:408-x2-product-brief.pdf|Product Brief]]
* [[:File:408-x2-x-gene-2-evaluation-kit-product-brief.pdf|APM883408-X2 X-Gene 2 X-C2 Evaluation Kit]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	X-Gene 2 APM883208-X2 - AppliedMicro#pcie +
core count	8 +
core voltage	0.9 V (9 dV, 90 cV, 900 mV) +
designer	AppliedMicro +
family	X-Gene +
first announced	September 2014 +
first launched	March 2015 +
full page name	apm/x-gene/apm883208-x2 +
has ecc memory support	true +
instance of	microprocessor +
io voltage	1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.5 V (25 dV, 250 cV, 2,500 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv8 +
isa family	ARM +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	March 2015 +
manufacturer	TSMC +
market segment	Server +
max junction temperature	363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory	262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth	27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels	2 +
max sata ports	6 +
max usb ports	2 +
microarchitecture	Shadowcat +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	APM883208-X2 +
name	APM883208-X2 +
process	28 nm (0.028 μm, 2.8e-5 mm) +
series	X-Gene 2 +
supported memory type	DDR3-1866 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	8 +
turbo frequency	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +