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== Overview ==
 
== Overview ==
−
Socket AM5 is a zero insertion force, lever actuated, {{wp|Surface-mount technology|surface-mount}} [[land grid array]] socket for use with a 1718-contact, 0.81 mm × 0.94 mm interstitial pitch, organic land grid array CPU package.
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{{future information}}
 +
 
 +
Socket AM5 is a zero insertion force, lever actuated, [[wikipedia:Surface-mount technology|surface-mount]] [[land grid array]] socket for use with a 1718-contact, 0.81 mm × 0.94 mm interstitial pitch, organic land grid array CPU package.
  
 
The following AMD processor families use Socket AM5:
 
The following AMD processor families use Socket AM5:
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The substrate has two keying notches preventing it from being inserted rotated into the socket, or incidentally into {{\\|Socket F}} or {{\\|Socket C32}}, two much older AMD sockets for LGA packages of the same size. Different keying options for future models are not evident, in any case AM5 packages are also electrically keyed by pin [[#AM5R1|AM5R1]] and Socket AM5 motherboards are not supposed to power up the socket if an incompatible processor is installed.<!--AMD-57012 Sec 12.3--> A triangular symbol on both sides of the substrate marks the location of pin A1, with corresponding markings on the socket.
 
The substrate has two keying notches preventing it from being inserted rotated into the socket, or incidentally into {{\\|Socket F}} or {{\\|Socket C32}}, two much older AMD sockets for LGA packages of the same size. Different keying options for future models are not evident, in any case AM5 packages are also electrically keyed by pin [[#AM5R1|AM5R1]] and Socket AM5 motherboards are not supposed to power up the socket if an incompatible processor is installed.<!--AMD-57012 Sec 12.3--> A triangular symbol on both sides of the substrate marks the location of pin A1, with corresponding markings on the socket.
  
−
Owing to the increase of contacts from 1331 on Socket AM4 to 1718, AM5 packages have a higher contact density with the same pitch as {{\\|Socket SP5}}, no components on the bottom side, and a redesigned lid a.k.a. integrated heat spreader which arcs over some of the top side {{wp|decoupling capacitor}}s providing more space for components.
+
Owing to the increase of contacts from 1331 on Socket AM4 to 1718, AM5 packages have a higher contact density with the same pitch as {{\\|Socket SP5}}, no components on the bottom side, and a redesigned lid a.k.a. integrated heat spreader which arcs over some of the top side [[wikipedia:Decoupling capacitor|decoupling capacitors]] providing more space for components.
  
 
AM5 processors are {{abbr|SoC}}s with an integrated controller hub so Socket AM5 pins out various low speed interfaces. The {{abbr|LPC}} interface present on the prior generation was deprecated in favor of {{abbr|SPI/ESPI}}. These busses are generally used to access firmware ({{abbr|PSP}} ROM and BIOS) i.e. flash memory, and a {{abbr|TPM}}. It is worth noting that the PSP can also provide TPM services. Added were {{abbr|I<sup>3</sup>C}}, and {{abbr|DMIC}} e.g. for Wake-On-Voice.
 
AM5 processors are {{abbr|SoC}}s with an integrated controller hub so Socket AM5 pins out various low speed interfaces. The {{abbr|LPC}} interface present on the prior generation was deprecated in favor of {{abbr|SPI/ESPI}}. These busses are generally used to access firmware ({{abbr|PSP}} ROM and BIOS) i.e. flash memory, and a {{abbr|TPM}}. It is worth noting that the PSP can also provide TPM services. Added were {{abbr|I<sup>3</sup>C}}, and {{abbr|DMIC}} e.g. for Wake-On-Voice.
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The force frame and stiffener frame are stamped out of 1.2&nbsp;mm thick stainless steel sheets. The cam lever is made from 2.5&nbsp;mm stainless steel wire. The force frame has a window allowing the top of the CPU package lid to protrude for contact with the heatsink. When closed and actuated with the cam lever it applies a load to the flanges on the sides of the lid. Markings include the name of the socket, supplier, a triangular pin A1 identifier, and a lot code on the force frame or stiffener frame. The force frame is hinged to the stiffener frame.
 
The force frame and stiffener frame are stamped out of 1.2&nbsp;mm thick stainless steel sheets. The cam lever is made from 2.5&nbsp;mm stainless steel wire. The force frame has a window allowing the top of the CPU package lid to protrude for contact with the heatsink. When closed and actuated with the cam lever it applies a load to the flanges on the sides of the lid. Markings include the name of the socket, supplier, a triangular pin A1 identifier, and a lot code on the force frame or stiffener frame. The force frame is hinged to the stiffener frame.
  
−
The stiffener frame has a window fitting the socket housing and incorporates a latch securing the lever in the actuated position. Four {{wp|Captive fastener|captive screws}} with {{wp|Unified Thread Standard|#6-32}} thread and {{wp|Torx}} drive mount the stiffener frame to {{wp|Swage_nut|self-clinching PEM nuts}} protruding up from the backplate through holes in the {{abbr|PCB}}. Backplates with different nut heights are available to account for different PCB thicknesses. Two 0.18&nbsp;mm thick insulating sheets in the shape of these parts separate them from the PCB.
+
The stiffener frame has a window fitting the socket housing and incorporates a latch securing the lever in the actuated position. Four [[wikipedia:Captive fastener|captive screws]] with [[wikipedia:Unified Thread Standard|#6-32]] thread and [[wikipedia:Torx|Torx]] drive mount the stiffener frame to [[wikipedia:Swage_nut|self-clinching PEM nuts]] protruding up from the backplate through holes in the {{abbr|PCB}}. Backplates with different nut heights are available to account for different PCB thicknesses. Two 0.18&nbsp;mm thick insulating sheets in the shape of these parts separate them from the PCB.
  
 
Like {{\\|Socket SP3}} and {{\\|Socket SP5|SP5}} the SAM apparently includes an external cap protecting the contact springs when no processor is installed.
 
Like {{\\|Socket SP3}} and {{\\|Socket SP5|SP5}} the SAM apparently includes an external cap protecting the contact springs when no processor is installed.
  
−
The socket housing is an injection-molded plastic part, likely made of black {{wp|liquid-crystal polymer}}, and ships with a cover cap made of the same material which protects the contact springs and facilitates pick-and-place operation with a vacuum nozzle during board assembly. The housing outline is asymmetric, preventing the SAM and cover cap from being installed rotated. The walls have finger access cut-outs, keying features matching those on the CPU package, and a chamfered corner locating pin A1. Four undercut steps on the outside and an alignment hole suggest corresponding latches and an alignment peg on the cover cap. The springs extend into a J-lead at the bottom of the housing with solder balls attached for {{wp|Surface-mount technology|surface mounting}}. Standoffs limit the distance to the PCB.
+
The socket housing is an injection-molded plastic part, likely made of black [[wikipedia:Liquid-crystal_polymer|liquid crystal polymer]], and ships with a cover cap made of the same material which protects the contact springs and facilitates pick-and-place operation with a vacuum nozzle during board assembly. The housing outline is asymmetric, preventing the SAM and cover cap from being installed rotated. The walls have finger access cut-outs, keying features matching those on the CPU package, and a chamfered corner locating pin A1. Four undercut steps on the outside and an alignment hole suggest corresponding latches and an alignment peg on the cover cap. The springs extend into a J-lead at the bottom of the housing with solder balls attached for [[wikipedia:Surface-mount technology|surface mounting]]. Standoffs limit the distance to the PCB.
  
 
=== Heatsink ===
 
=== Heatsink ===
−
The heatsink can be clipped onto a two-part retention frame made of plastic. The two-part design permits components closer to the socket and smaller boards. Each of the identical parts has an alignment peg preventing it from being installed rotated on the PCB which has correspondingly shaped through-holes. Two screws with {{wp|Unified Thread Standard|#6-32}} thread (like PC case screws; the closest metric substitute is the non-standard {{wp|ISO metric screw thread|M3.5×0.8}} thread) mount each part to a second set of taller PEM nuts, spaced 54&nbsp;mm × 90&nbsp;mm apart, which protrude up through the PCB from the backplate. Their height is some 5&nbsp;mm leaving 4.34&nbsp;mm headroom to the top of the package lid in the actuated socket. Heavier heatsinks can be attached directly to the backplate with four captive spring screws on the heatsink after removal of the retention frame. The positions of the retention frame latches and heatsink nuts are symmetric so the heatsink can be rotated 180 degrees.
+
The heatsink can be clipped onto a two-part retention frame made of plastic. The two-part design permits components closer to the socket and smaller boards. Each of the identical parts has an alignment peg preventing it from being installed rotated on the PCB which has correspondingly shaped through-holes. Two screws with [[wikipedia:Unified Thread Standard|#6-32]] thread (like PC case screws; the closest metric substitute is the non-standard [[wikipedia:ISO_metric_screw_thread|M3.5×0.8]] thread) mount each part to a second set of taller PEM nuts, spaced 54&nbsp;mm × 90&nbsp;mm apart, which protrude up through the PCB from the backplate. Their height is some 5&nbsp;mm leaving 4.34&nbsp;mm headroom to the top of the package lid in the actuated socket. Heavier heatsinks can be attached directly to the backplate with four captive spring screws on the heatsink after removal of the retention frame. The positions of the retention frame latches and heatsink nuts are symmetric so the heatsink can be rotated 180 degrees.
  
 
The heatsink attachment facilities and the height of the processor in the actuated socket, 7.98 ± 0.60 mm from the top of the PCB to the top of the lid, are in line with {{\\|Socket AM4}} so heatsinks for that socket can be used.
 
The heatsink attachment facilities and the height of the processor in the actuated socket, 7.98 ± 0.60 mm from the top of the PCB to the top of the lid, are in line with {{\\|Socket AM4}} so heatsinks for that socket can be used.
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== Feature Summary ==
 
== Feature Summary ==
 
* Lidded [[land grid array]] package, 40&nbsp;mm × 40&nbsp;mm
 
* Lidded [[land grid array]] package, 40&nbsp;mm × 40&nbsp;mm
−
** 1718 contacts in a 44 × 41 grid, 0.81&nbsp;mm × 0.94&nbsp;mm interstitial pitch
+
** 1718 contacts in a 44 × 40 grid, 0.81&nbsp;mm × 0.94&nbsp;mm interstitial pitch
 
** Organic substrate, [[flip chip]] die attachment
 
** Organic substrate, [[flip chip]] die attachment
  
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** 4 × {{abbr|I<sup>3</sup>C}}/{{abbr|I<sup>2</sup>C}}
 
** 4 × {{abbr|I<sup>3</sup>C}}/{{abbr|I<sup>2</sup>C}}
 
** 2 × {{abbr|SMBus}}
 
** 2 × {{abbr|SMBus}}
−
** Up to 55 {{abbr|GPIO}}s
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** {{abbr|GPIO}}
 
** Sideband Interface ({{abbr|SB-TSI}})
 
** Sideband Interface ({{abbr|SB-TSI}})
−
** Serial VID Interface ({{amd|SVI3}})
+
** Serial VID Interface (SVI3)
 
** {{abbr|JTAG}}
 
** {{abbr|JTAG}}
  
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{{comp table start}}
 
{{comp table start}}
 
<table class="comptable sortable">
 
<table class="comptable sortable">
−
{{comp table header|cols|Family|Microarch.|Cores|Threads|%L2$|%L3$|%Base|%Turbo|Memory|%{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}
+
{{comp table header|cols|Family|Microarch.|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}
 
{{#ask: [[Category:microprocessor models by amd]] [[socket::~*AM5]]
 
{{#ask: [[Category:microprocessor models by amd]] [[socket::~*AM5]]
 
|?full page name
 
|?full page name
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|userparam=15
 
|userparam=15
 
|mainlabel=-
 
|mainlabel=-
−
|valuesep=,&#32;
+
|valuesep=,<br/>
 
}}
 
}}
 
{{comp table count|ask=[[Category:microprocessor models by amd]] [[socket::~*AM5]]}}
 
{{comp table count|ask=[[Category:microprocessor models by amd]] [[socket::~*AM5]]}}
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== Pin Map ==
 
== Pin Map ==
−
[[File:Socket AM5 pinmap.svg|800px]]
+
{{empty section}}
−
 
 
−
Socket AM5 pinout, top view. Click to flip and rotate.
 
  
 
=== Pin Description ===
 
=== Pin Description ===
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|MAA/MAB/MBA/MBB_DQS_H/L[4:0]||DRAM Channel A/B Subchannel A/B Data Strobe Differential Pair
 
|MAA/MAB/MBA/MBB_DQS_H/L[4:0]||DRAM Channel A/B Subchannel A/B Data Strobe Differential Pair
 
|-
 
|-
−
|MAA0/MAB0/MBA0/MBB0_CLK_H/L[1:0]<br />MAA1/MAB1/MBA1/MBB1_CLK_H/L[1:0]||DRAM Channel A/B DIMM 0/1 Subchannel A/B Differential Clock
+
|MAA0/MAB0/MBA0/MBB0_CLK_H/L[1:0]<br/>MAA1/MAB1/MBA1/MBB1_CLK_H/L[1:0]||DRAM Channel A/B DIMM 0/1 Subchannel A/B Differential Clock
 
|-
 
|-
−
|MAA0/MAB0/MBA0/MBB0_CS_L[1:0]<br />MAA1/MAB1/MBA1/MBB1_CS_L[1:0]||DRAM Channel A/B DIMM 0/1 Subchannel A/B Chip Select
+
|MAA0/MAB0/MBA0/MBB0_CS_L[1:0]<br/>MAA1/MAB1/MBA1/MBB1_CS_L[1:0]||DRAM Channel A/B DIMM 0/1 Subchannel A/B Chip Select
 
|-
 
|-
 
|PCIE_RXP/RXN[27:0]||PCIe Receive Data Differential Pairs
 
|PCIE_RXP/RXN[27:0]||PCIe Receive Data Differential Pairs
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|DP_STEREOSYNC||StereoSync output for shutter glasses
 
|DP_STEREOSYNC||StereoSync output for shutter glasses
 
|-
 
|-
−
|USBC(0-2)_RX1P/RX1N||USB Port 0-2 {{wp|USB-C}} Receive Differential Pairs or DisplayPort Transmitter Lane 3
+
|USBC(0-2)_RX1P/RX1N||USB Port 0-2 USB-C Receive Differential Pairs or DisplayPort Transmitter Lane 3
 
|-
 
|-
 
|USBC(0-2)_TX1P/TX1N||USB Port 0-2 USB-C Transmit Differential Pairs or DisplayPort Transmitter Lane 2
 
|USBC(0-2)_TX1P/TX1N||USB Port 0-2 USB-C Transmit Differential Pairs or DisplayPort Transmitter Lane 2
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|USBC(0-2)_TX2P/TX2N||USB Port 0-2 USB-C Transmit Differential Pairs or DisplayPort Transmitter Lane 1
 
|USBC(0-2)_TX2P/TX2N||USB Port 0-2 USB-C Transmit Differential Pairs or DisplayPort Transmitter Lane 1
 
|-
 
|-
−
|USB(0-3)_RXP/RXN||USB Port 0-3 USB3 Super Speed Receive Differential Pairs
+
|USB3_RXP/RXN||USB Port 3 USB3 Super Speed Receive Differential Pairs
 
|-
 
|-
−
|USB(0-3)_TXP/TXN||USB Port 0-3 USB3 Super Speed Transmit Differential Pairs
+
|USB3_TXP/TXN||USB Port 3 USB3 Super Speed Transmit Differential Pairs
 
|-
 
|-
−
|USBC(0-2)_DP/DN<br />USB(0-4)_DP/DN||USB Port 0-4 USB2 I/O Differential Pairs
+
|USB(0-4)_DP/DN||USB Port 0-4 USB2 I/O Differential Pairs
 
|-
 
|-
−
|USBC(0-1)_SBRX/SBTX||USB Port 0-1 USB4 Sideband Interface (alt. func. of DP1_AUX, DP2_AUX)
+
|USBC0/USBC1_SBRX/SBTX||USB Port 0-1 USB4 Sideband Interface Differential Pairs (alt. func. of DP1_AUX, DP2_AUX)
 
|-
 
|-
−
|USBC_I2C_SCL||{{abbr|I<sup>2</sup>C}} Clock for USB-C PD Control
+
|USBC_I2C_SCL||I<sup>2</sup>C Clock for USB-C PD Control
 
|-
 
|-
 
|USBC_I2C_SDA||I<sup>2</sup>C Data for USB-C PD Control
 
|USBC_I2C_SDA||I<sup>2</sup>C Data for USB-C PD Control
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|USB_OC(0-3)_L||USB Over Current signal from USB connector
 
|USB_OC(0-3)_L||USB Over Current signal from USB connector
 
|-
 
|-
−
|AZ_BITCLK||{{wp|Intel High Definition Audio|Azalia HD Audio}} Interface Bit Clock
+
|AZ_BITCLK||[[wikipedia:Intel High Definition Audio|Azalia HD Audio]] Interface Bit Clock
 
|-
 
|-
 
|AZ_RST_L||HDA Reset
 
|AZ_RST_L||HDA Reset
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|SPI_ROM_GNT||SPI ROM Grant
 
|SPI_ROM_GNT||SPI ROM Grant
 
|-
 
|-
−
|ESPI_CLK||{{abbr|ESPI}} Clock Output
+
|ESPI_CLK||[[wikipedia:Serial Peripheral Interface|Enhanced SPI]] Clock Output
 
|-
 
|-
 
|ESPI_DAT[3:0]||ESPI Data[0], Data[1:0], Data[3:0] Input/Output
 
|ESPI_DAT[3:0]||ESPI Data[0], Data[1:0], Data[3:0] Input/Output
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|-
 
|-
 
|EGPIO*||Enhanced GPIO for I/O only
 
|EGPIO*||Enhanced GPIO for I/O only
−
|-
 
−
|GENINT(1-2)_L||Generic Interrupt Request
 
 
|-
 
|-
 
|GPP_CLK(0-5)P/N||100&nbsp;MHz Differential PCIe Reference Clock Outputs
 
|GPP_CLK(0-5)P/N||100&nbsp;MHz Differential PCIe Reference Clock Outputs
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|-
 
|-
 
|PWR_BTN_L||Power Button Input; Requests sleep state or causes wake event
 
|PWR_BTN_L||Power Button Input; Requests sleep state or causes wake event
−
|-
 
−
|PWROK||
 
 
|-
 
|-
 
|RESET_L||Reset signal
 
|RESET_L||Reset signal
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|SID||Sideband Interface Data
 
|SID||Sideband Interface Data
 
|-
 
|-
−
|THERMTRIP_L||{{x86|thermal protection|Temperature Trip}} Output
+
|THERMTRIP_L||{{x86|Thermal protection|Temperature Trip}} Output
−
|-
 
−
|DBREQ_L||Debug Request input to JTAG controller
 
 
|-
 
|-
 
|TCK||{{abbr|JTAG}} Clock
 
|TCK||{{abbr|JTAG}} Clock
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|TEST*||Test/Debug signals
 
|TEST*||Test/Debug signals
 
|-
 
|-
−
|CCD_ANALOG_TEST||
+
|SVC||Serial VID Clock for VDDCR/VDDCR_SOC regulator
−
|-
 
−
|PCC_L||
 
−
|-
 
−
|SVC||Serial VID Clock; ({{amd|SVI3}}) interface to VDDCR/VDDCR_SOC regulator
 
 
|-
 
|-
 
|SVD||Serial VID Data
 
|SVD||Serial VID Data
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|-
 
|-
 
|VDD_MISC_S5_SENSE||Differential (with VSS_SENSE_B) feedback for VDD_MISC_S5 regulator
 
|VDD_MISC_S5_SENSE||Differential (with VSS_SENSE_B) feedback for VDD_MISC_S5 regulator
−
|-
 
−
|VSS||Ground
 
 
|-
 
|-
 
|VSS_SENSE_A||VSS Sense pin for VDDCR/VDDCR_SOC regulator
 
|VSS_SENSE_A||VSS Sense pin for VDDCR/VDDCR_SOC regulator
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|-
 
|-
 
|{{vanchor|AM5R1}}||Processor family revision identifier; NC = Not connected, VSS = connected to VSS on the package<br/><table class="wikitable"><tr><th>Processor</th><th>AM5R1</th></tr><tr><td>Type-1/2/3</td><td>NC</td></tr></table><!--AMD-57012-0.70 Sec 12.3-->
 
|{{vanchor|AM5R1}}||Processor family revision identifier; NC = Not connected, VSS = connected to VSS on the package<br/><table class="wikitable"><tr><th>Processor</th><th>AM5R1</th></tr><tr><td>Type-1/2/3</td><td>NC</td></tr></table><!--AMD-57012-0.70 Sec 12.3-->
−
|-
 
−
|AUX(0-5)_RST_L||
 
−
|-
 
−
|OSCIN||
 
 
|-
 
|-
 
|RSVD||Reserved
 
|RSVD||Reserved
−
|-
 
−
|SMU_ZVDD_ODPR(0-2)||
 
−
|-
 
−
|TMU_CLK_OUT||
 
 
|}
 
|}
  

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Retrieved from "https://en.wikichip.org/wiki/amd/packages/socket_am5"
Facts about "Socket AM5 - Packages - AMD"
RDF feed
designerAMD +
instance ofpackage +
market segmentDesktop +
microarchitectureZen 4 +
nameSocket AM5 +
packageAM5 +
package contacts1,718 +
package length40 mm (4 cm, 1.575 in) +
package pitch0.81 mm (0.0319 in) + and 0.94 mm (0.037 in) +
package typeFC-OLGA +
package width40 mm (4 cm, 1.575 in) +
socketSocket AM5 +
tdp170 W (170,000 mW, 0.228 hp, 0.17 kW) +