Editing amd/epyc embedded

{{amd title|EPYC Embedded}}
{{ic family
| title             = AMD EPYC Embedded
| image             = epyc embedded logo.png
| caption           = EPYC Embedded logo
| developer         = AMD
| manufacturer      = GlobalFoundries
| type              = System on chips
| first announced   = February 22, 2018
| first launched    = February 22, 2018
| arch              = Embedded x86 SoCs
| isa               = x86-64
| microarch         = Zen
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 1,500 MHz
| clock max         = 2,700 MHz
| package           = 
| socket            = Socket SP4
| socket 2          = Socket SP4r2

| succession       = Yes
| predecessor      = Opteron
| predecessor link = amd/opteron
| successor        = 
| successor link   = 
}}
'''EPYC Embedded''' is a family of {{arch|64}} multi-core [[x86]] embedded microprocessors designed and introduced by [[AMD]]. Those processors are primarily aimed at networking, storage, and edge computing devices. EPYC Embedded effectively succeeded the {{amd|Opteron}} A1100 series of embedded microprocessors (although those were actually based on [[ARM]], not [[x86]]).

== Overview ==
The EPYC Embedded family is a low-power variant of the {{amd|EPYC}} line that primarily marketed towards embedded devices such as networking, storage, and edge computing devices. Those parts have lower TDPs and come in a much smaller package allowing for denser integration.

== Members ==
=== 3000 Series (Zen) ===
{{see also|amd/cores/snowy_owl|amd/microarchitectures/zen|l1=Snowy Owl|l2=Zen µarch}}
Introduced in early 2018, the 3000 embedded series is based on the {{amd|Zen|Zen microarchitecture|l=arch}} using the same dies as the server {{amd|EPYC}} processors. 3000-series come in anywhere from [[4 cores|4]] to [[16 cores]] as well as with and without [[SMT]] support. Models with 8 or less cores come in a single-die configuration and uses a single-chip module {{amd|Package SP4r4}} while models with more than eight cores come in a dual-die configuration and use a multi-chip module {{amd|Package SP4}}. Both packages are ball grid arrays (BGAs) and are pin-compatible with each other. Geared toward embedded applications means those parts have lower TDP than their server counterparts. Depending on the die configuration, the features of the dual-die config are mostly double that of the single-die config.

* Dual-die Models
** '''Mem:''' Quad-channel 64-bit DDR4-2666 w/ ECC, up to 1 TiB
** '''I/O:''' x64 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 16 SATA ports and up to 10 x 10GbE  ports 
** '''TDP:''' 65-100 W
* Single-die Models
** '''Mem:''' Dual-channel 64-bit DDR4-2666/2133 w/ ECC, up to 512 GiB
** '''I/O:''' x32 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 8 SATA ports and up to 4 x 10GbE  ports
** '''TDP:''' 35-50 W

The ISA and Technology applies to all models.

* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
* '''Tech:''' {{amd|Precision Boost}}, 2-way [[SMT]], {{amd|AMD-Vi}}, {{amd|AMD-V}}, {{amd|Secure Memory Encryption}} (SME), and {{amd|Secure Encrypted Virtualization}} (SEV)

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           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc4 tc5 tc9 tc10 tc12">
{{comp table header|main|11:List EPYC Embedded 3000-Series Processors}}
{{comp table header|cols|Price|Launched|Cores|Thread|L2$|L3$|%TDP|%Base|%Turbo (Max)|Memory|PCIe Lanes}}
{{comp table header|lsep|11:Single-Chip Package (1 die)}}
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen]] [[family::EPYC Embedded]] [[core count::<8]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |?Has subobject.max pcie lanes
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
}}
{{comp table header|lsep|11:Multi-Chip Package (2 dies)}}
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen]] [[family::EPYC Embedded]] [[core count::>9]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |?Has subobject.max pcie lanes
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[microarchitecture::Zen]] [[family::EPYC Embedded]]}}
</table>
{{comp table end}}

== Documents ==
* [[:File:3000-Family-Product-Brief.pdf|EPYC 3000 series Product Brief]]

== See also ==
* AMD {{amd|Ryzen Embedded}}
* Intel {{intel|Xeon D}}
* Cavium {{cavium|ThunderX2}}
designer	AMD +
first announced	February 22, 2018 +
first launched	February 22, 2018 +
full page name	amd/epyc embedded +
instance of	system on a chip family +
instruction set architecture	x86-64 +
main designer	AMD +
manufacturer	GlobalFoundries +
microarchitecture	Zen +
name	AMD EPYC Embedded +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket SP4 + and Socket SP4r2 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +