Editing amd/epyc

{{amd title|EPYC}}
{{ic family
| title             = AMD EPYC
| image             = amd epyc logo.png
| caption           = EPYC logo
| developer         = AMD
| manufacturer      = GlobalFoundries
| manufacturer 2    = TSMC
| type              = System on chips
| first announced   = May 16, 2017
| first launched    = June 20, 2017
| arch              = High-performance Server SOCs
| isa               = x86-64
| microarch         = Zen
| microarch 2       = Zen 2
| microarch 3       = Zen 3
| word              = 64 bit
| proc              = 14 nm
| proc 2            = 7 nm
| tech              = CMOS
| clock min         = 2,000 MHz
| clock max         = 2,400 MHz
| package           = FCLGA-4094
| socket            = Socket SP3

| succession       = Yes
| predecessor      = Opteron
| predecessor link = amd/opteron
| successor        = 
| successor link   = 
}}
'''EPYC''' (pronounced ''epic'') is a family of {{arch|64}} [[x86]] high-performance server [[multiprocessors]] introduced by [[AMD]] in 2017 as the successor to the {{amd|Opteron}} family.

== Overview ==
[[File:lisa announces epyc.png|right|thumb|Lisa Su introducing EPYC.]]
EPYC is AMD's flagship mainstream server microprocessors. It was originally announced during AMD's Financial Analyst Day on May 16, [[2017]]. EPYC replaces the previous {{amd|Opteron}} server family with the introduction of the {{amd|Zen|l=arch}} microarchitecture which was introduced early [[2017]] for the mainstream market. EPYC processors support 1-way and 2-way [[multiprocessing]].

First generation EPYC processors, the 7001 series codenamed "{{amd|Naples|l=core}}", are based on the {{amd|Zen|l=arch}} microarchitecture and were launched in June [[2017]]. Using chips manufactured on a [[GlobalFoundries]] [[14 nm process]], these microprocessors range from [[8 cores|eight]] to [[32 cores|thirty-two]] cores. In mid-[[2019]], AMD introduced the second EPYC generation, the 7002 "{{amd|Rome|l=core}}" series, which doubled the number of cores to [[64 cores|sixty-four]]. It was followed by the {{amd|Zen 3|l=arch}}-based 7003 series codenamed "{{amd|Milan|l=core}}" in March [[2021]].

=== Codenames ===
{| class="wikitable"
|-
! Introduction !! Codename !! Microarchitecture !! Socket !! Process !! Cores
|-
| June, [[2017]] || {{amd|Naples|l=core}} || {{amd|Zen|l=arch}} || {{amd|Socket SP3|l=pack}} || [[14 nm]] || [[8 cores|8]]-[[32 cores|32]]
|-
| August, [[2019]] || {{amd|Rome|l=core}} || {{amd|Zen 2|l=arch}} || {{amd|Socket SP3|l=pack}} || [[7 nm]] || [[8 cores|8]]-[[64 cores|64]]
|-
| March, [[2021]] || {{amd|Milan|l=core}} || {{amd|Zen 3|l=arch}} || {{amd|Socket SP3|l=pack}} || [[7 nm+]] || [[8 cores|8]]-[[64 cores|64]]
|-
| ? || {{amd|Genoa|l=core}} || {{amd|Zen 4|l=arch}} || ? || [[5 nm]] || ?
|}

== Naming scheme ==
{{chip identification
| title     =
| parts     = 6
| ex 1      = EPYC
| ex 2      = &nbsp;
| ex 3      = 7
| ex 4      = 70
| ex 5      = 2
| ex 6      = P
| desc 1    = <table style="text-align:left"><th colspan="2">Product Family</th>
<tr><td>EPYC</td></tr>
<tr><td>EPYC Embedded</td></tr>
</table>
| desc 3    = <table style="text-align:left"><th colspan="2">Product Series</th>
<tr><th>3xxx</th><td>Embedded SOC</td></tr>
<tr><th>7xxx</th><td>High-performance server CPU/SOC</td></tr>
</table>
| desc 4    = <table style="text-align:left"><th colspan="2">Product Model / Performance Level</th>
<tr><th>Fx/xF</th><td>Frequency optimized</td></tr>
<tr><th>Hx</th><td>[[HPC]]-optimized</td></tr>
</table>
| desc 5    = <table style="text-align:left"><th colspan="2">Generation</th>
<tr><th>1</th><td>First generation, 7001 "{{amd|Naples|l=core}}" series, {{amd|Zen|l=arch}} microarchitecture</td></tr>
<tr><th>2</th><td>Second generation, 7002 "{{amd|Rome|l=core}}" series, {{amd|Zen 2|l=arch}} microarchitecture</td></tr>
<tr><th>3</th><td>Third generation, 7003 "{{amd|Milan|l=core}}" series, {{amd|Zen 3|l=arch}} microarchitecture</td></tr>
</table>
| desc 6    = <table style="text-align:left"><th colspan="2">Feature Modifier</th>
<tr><th>(none)</th><td>1P, 2P</td></tr>
<tr><th>P</th><td>1P (single socket) only</td></tr>
</table>
}}

== Members ==
=== 7001 Series (Zen) ===
{{see also|amd/cores/naples|amd/microarchitectures/zen|l1=Naples|l2=Zen µarch}}
Introduced in June of [[2017]], first generation EPYC processors are based on the {{amd|Zen|l=arch}} architecture fabricated on GlobalFoundries' [[14 nm process]]. EPYC 7000 series effectively succeeds the previous {{amd|Opteron}} 6000 series. All models consist of four {{amd|Zen#Modules (Zeppelin)|Zeppelin dies|l=arch}}, providing support for up to octa-channel DDR4 ECC memory of up to 2400-2666 MT/s supporting up to 2 [[TiB]] of memory per socket (for up to 4 TiB in 2-way MP). Each processor has 128 [[PCIe]] lanes and non-P models also support two-way multiprocessing utilizing 64 PCIe lanes for this purpose from each CPU.

* All models support everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}

Additionally, all models support AMD's new {{amd|Secure Memory Encryption}} (SME), its subset TSME, and {{amd|Secure Encrypted Virtualization}} (SEV) security technologies.

It should be noted that for some models, there are two [[TDP]] values given because the TDP will depend on the memory rate used for the system (i.e., either 2666 MT/s or 2400 MT/s). The ''All Boost'' frequency is the {{amd|precision boost}} frequency that can be applied to all cores when they're all active. When less than 12 cores are active, however, the ''Max Boost'' frequency can be applied for even higher performance - provided there's sufficient thermal and electrical headroom.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc10 tc11 tc12">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="11">List of Zen-based EPYC Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="7">Main Specs</th><th colspan="6">Frequency</th></tr>
<tr class="comptable-header"><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>Threads</th><th>L3$</th><th>TDP</th><th>Memory</th><th>Base Frequency</th><th>All Boost</th><th>Max Boost</th></tr>
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Naples]] [[max cpu count:: 1]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency (13 cores)#GHz
 |?turbo frequency (1 core)#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (dual-socket)</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Naples]] [[max cpu count:: !1]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency (13 cores)#GHz
 |?turbo frequency (1 core)#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]]  [[core name::Naples]]}}
</table>
{{comp table end}}

=== 7002 Series (Zen 2) ===

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc10 tc11 tc12">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="12">List of Zen 2-based EPYC Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="8">Main Specs</th><th colspan="7">Frequency</th></tr>
<tr class="comptable-header"><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>Threads</th><th>L2$</th><th>L3$</th><th>TDP</th><th>Memory</th><th>Base Frequency</th><th>Max Boost</th></tr>
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Rome]] [[max cpu count:: 1]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (dual-socket)</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Rome]] [[max cpu count:: !1]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[HPC]]-optimized SKUs</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Rome]] [[part of::HPC-optimized SKUs]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">Frequency-optimized SKUs</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Rome]] [[max cpu count:: !1]] [[part of::Frequency-optimized SKUs]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]]  [[core name::Rome]]}}
</table>
{{comp table end}}

=== 7003 Series (Zen 3) ===
{{see also|amd/cores/milan|amd/microarchitectures/zen 3|l1=Milan|l2=Zen 3 µarch}}
The third generation of EPYC processors was launched on March 15, 2021. These processors are backwards compatible with motherboards for the EPYC 7002 series and have the same basic features. Development focused on microarchitectural improvements resulting in a 19% IPC uplift and higher efficiency. Other improvements include:

* Core Complex with 8 CPU cores sharing a 32 MiB L3 cache, i.e. twice as much L3 cache available to one core and lower inter-core latency.
* Coupled Infinity Fabric and memory clock for slightly lower memory latency now supported up to 1600 MHz (DDR4-3200).
* New 4- and 6-channel memory configuration options for better memory performance at reduced memory cost.
* I/O performance improvements.
* Third generation Secure Encrypted Virtualization with a new Secure Nested Paging extension to protect the confidentiality and also integrity of code and data in virtual machines.
* Control-flow Enforcement Technology / Shadow Stack, a countermeasure to security exploits redirecting the control flow to code fragments which happen to perform unintended operations useful to an attacker.
<br/>

<!-- NOTE:
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc10 tc11 tc12">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="12">List of Zen 3-based EPYC Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="8">Main Specs</th><th colspan="7">Frequency</th></tr>
<tr class="comptable-header"><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>Threads</th><th>L2$</th><th>L3$</th><th>TDP</th><th>Memory</th><th>Base Frequency</th><th>Max Boost</th></tr>
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Milan]] [[max cpu count:: 1]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (dual-socket)</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Milan]] [[max cpu count:: !1]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">Frequency-optimized SKUs</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Milan]] [[max cpu count:: !1]] [[part of::Frequency-optimized SKUs]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?l2$ size#MiB
 |?l3$ size#MiB
 |?tdp
 |?supported memory type
 |?base frequency#GHz
 |?turbo frequency#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]]  [[core name::Milan]]}}
</table>
{{comp table end}}

== Documents ==
* [[:File:AMD EPYC 7000-series Product Brief.pdf|AMD EPYC 7000-series Product Brief]], June 2017
* [[:File:amd epyc performance brief.pdf|AMD EPYC Performance Brief]], June 2017
* [[:File:amd epyc solution brief.pdf|AMD EPYC Solution Brief]], June 2017

== See also ==
* Intel
{{collist
| count = 2
| style = padding-left: 30px
|
* {{intel|Xeon E5}}
* {{intel|Xeon E7}}
* {{intel|Xeon Bronze}}
* {{intel|Xeon Silver}}
}}
* Qualcomm
** {{qualcomm|Centriq}}
* Cavium
** {{cavium|ThunderX2}}
designer	AMD +
first announced	May 16, 2017 +
first launched	June 20, 2017 +
full page name	amd/epyc +
instance of	system on a chip family +
instruction set architecture	x86-64 +
main designer	AMD +
manufacturer	GlobalFoundries + and TSMC +
microarchitecture	Zen +, Zen 2 +, Zen 3 + and Zen 4 +
name	AMD EPYC +
package	FCLGA-4094 + and FCLGA-? +
process	14 nm (0.014 μm, 1.4e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +
socket	Socket SP3 + and Socket SP5 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +