Editing amd/epyc/7281

{{amd title|EPYC 7281}}
{{chip
|name=EPYC 7281
|no image=Yes
|designer=AMD
|manufacturer=GlobalFoundries
|model number=7281
|market=Server
|first announced=June 20, 2017
|first launched=June 20, 2017
|release price=$650
|family=EPYC
|series=7000
|locked=No
|frequency=2,100 MHz
|turbo frequency1=2,700 MHz
|turbo frequency2=2,700 MHz
|turbo frequency3=2,700 MHz
|turbo frequency4=2,700 MHz
|turbo frequency5=2,700 MHz
|turbo frequency6=2,700 MHz
|turbo frequency7=2,700 MHz
|turbo frequency8=2,700 MHz
|turbo frequency9=2,700 MHz
|turbo frequency10=2,700 MHz
|turbo frequency11=2,700 MHz
|turbo frequency12=2,700 MHz
|turbo frequency13=2,700 MHz
|turbo frequency14=2,700 MHz
|turbo frequency15=2,700 MHz
|turbo frequency16=2,700 MHz
|clock multiplier=21
|isa=x86-64
|isa family=x86
|microarch=Zen
|core name=Naples
|core family=23
|core model=1
|core stepping=B2
|process=14 nm
|transistors=19,200,000,000
|technology=CMOS
|die area=213 mm²
|mcp=Yes
|die count=4
|word size=64 bit
|core count=16
|thread count=32
|max cpus=2
|max memory=2 TiB
|tdp=155 W
|tdp 2=170 W
|tcase min=0 °C
|tcase max=85 °C
|package name 1=amd,socket_sp3
}}
'''EPYC 7281''' is a dual-socket {{arch|64}} [[16-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7281 has a base frequency of 2.1 GHz with a turbo frequency of 2.7 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.


{{unknown features}}

== Cache ==
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
{{cache size
|l1 cache=1.5 MiB
|l1i cache=1 MiB
|l1i break=16x64 KiB
|l1i desc=4-way set associative
|l1d cache=512 KiB
|l1d break=16x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=8 MiB
|l2 break=16x512 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=32 MiB
|l3 break=4x8 MiB
|l3 desc=16-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|type 2=DDR4-2400
|ecc=Yes
|max mem=2 TiB
|controllers=8
|channels=8
|max bandwidth=158.95 GiB/s
|bandwidth schan=19.89 GiB/s
|bandwidth dchan=39.72 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth ochan=158.95 GiB/s
|bandwidth hchan=119.21 GiB/s
}}

In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 317.9 GiB/s.

== Expansions ==
The EPYC 7351P has 128 Gen 3 PCIe lanes.
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 128
| pcie config        = 8x16
| pcie config 2      = 32x4
| sata revision      = 
| sata ports         = 
| usb revision       = 
| usb revision 2     = 
| usb ports          = 
| usb rate           = 
| uart               = 
| uart ports         = 
| gp io              = 
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=Yes
|avx=Yes
|avx2=Yes

|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=Yes
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=No
|tbmt3=No
|bpt=No
|eist=No
|sst=No
|flex=No
|fastmem=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=No
|txt=No
|ht=No
|vpro=No
|vtx=No
|vtd=No
|ept=No
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=Yes
|amdv=Yes
|amdsme=Yes
|amdtsme=Yes
|amdsev=Yes
|rvi=No
|smt=Yes
|sensemi=Yes
|xfr=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7281 - AMD#io +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
clock multiplier	21 +
core count	16 +
core family	23 +
core model	1 +
core name	Naples +
core stepping	B2 +
designer	AMD +
die area	213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count	4 +
family	EPYC +
first announced	June 20, 2017 +
first launched	June 20, 2017 +
full page name	amd/epyc/7281 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	false +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	4-way set associative +
l1i$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description	8-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	16-way set associative +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	June 20, 2017 +
manufacturer	GlobalFoundries +
market segment	Server +
max case temperature	358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels	8 +
max pcie lanes	128 +
microarchitecture	Zen +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	7281 +
name	EPYC 7281 +
package	FCLGA-4094 + and SP3 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 650.00 (€ 585.00, £ 526.50, ¥ 67,164.50) +
series	7000 +
smp max ways	2 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-2666 + and DDR4-2400 +
tdp	155 W (155,000 mW, 0.208 hp, 0.155 kW) + and 170 W (170,000 mW, 0.228 hp, 0.17 kW) +
technology	CMOS +
thread count	32 +
transistor count	19,200,000,000 +
turbo frequency (10 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (11 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (12 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (13 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (14 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (15 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (16 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (1 core)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (2 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (3 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (4 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (5 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (6 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (7 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (8 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (9 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +