Editing amd/duron/dhm0950aqs1b

{{amd title|Duron 950 (Camaro)}}
{{chip
| name                = Duron 950
| no image            = Yes
| image               = 
| image size          = 
| caption             = 
| designer            = AMD
| manufacturer        = AMD
| model number        = Duron 950
| part number         = DHM0950AQS1B
| part number 2       = 
| part number 3       = 
| part number 4       = 
| market              = Mobile
| first announced     = November 12, 2001
| first launched      = November 12, 2001
| last order          = 
| last shipment       = 

| family              = Duron
| series              = Duron Mobile
| locked              = Yes
| frequency           = 950 MHz
| bus type            = FSB
| bus speed           = 100 MHz
| bus rate            = 200 MT/s
| clock multiplier    = 9.5
| cpuid               = 670

| microarch           = K7
| platform            = 
| chipset             = 
| core name           = Morgan
| core family         = 6
| core model          = 7
| core stepping       = 0
| core stepping 2     = 
| process             = 180 nm
| transistors         = 25,180,000
| technology          = CMOS
| die size            = 105.68 mm²
| word size           = 32 bit
| core count          = 1
| thread count        = 1
| max cpus            = 1
| max memory          = 4 GiB


| power               = 
| v core              = 1.45 V
| v core tolerance    = 0.1 V
| v io                = 2.5 V
| v io tolerance      = 0.25 V
| sdp                 = 
| tdp                 = 25 W
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 0 °C
| tcase max           = 95 °C
| tstorage min        = -40 °C
| tstorage max        = 100 °C

| packaging           = Yes
| package 0           = CPGA-453
| package 0 type      = CPGA
| package 0 pins      = 453
| package 0 pitch     = 1.27 mm
| package 0 width     = 49.53 mm
| package 0 length    = 49.53 mm
| package 0 height    = 1.422 m
| socket 0            = Socket A
| socket 0 type       = PGA-462
}}
The '''Mobile Duron 950''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in late 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 950 MHz with a bus capable of 200 MT/s with a max TDP of 25 W.

== Cache ==
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
{{cache info
|l1i cache=64 KiB
|l1i break=1x64 KiB
|l1i desc=2-way set associative
|l1i extra=
|l1d cache=64 KiB
|l1d break=1x64 KiB
|l1d desc=2-way set associative
|l1d extra=
|l2 cache=64 KiB
|l2 break=1x64 KiB
|l2 desc=16-way set associative
|l2 extra=
|l3 cache=
|l3 break=
|l3 desc=
|l3 extra=
}}

== Graphics ==
This SoC has no integrated graphics processing unit.

== Features == 
{{x86 features
| em64t       = 
| nx          = 
| txt         = 
| tsx         = 
| vpro        = 
| ht          = 
| tbt1        =
| tbt2        = 
| bpt         = 
| vt-x        = 
| vt-d        = 
| ept         = 
| mmx         = Yes
| emmx        = Yes
| 3dnow       = Yes
| e3dnow      = Yes
| sse         = Yes
| sse2        = 
| sse3        = 
| ssse3       = 
| sse4        = 
| sse4.1      = 
| sse4.2      = 
| aes         = 
| pclmul      = 
| avx         = 
| avx2        = 
| bmi         = 
| bmi1        = 
| bmi2        = 
| f16c        = 
| fma3        = 
| mpx         = 
| sgx         = 
| eist        = 
}}
* [[has feature::Halt State]]
* [[has feature::Sleep State]]

== Documents ==
=== DataSheet ===
* [[:File:Mobile AMD Duron Processor Model 7 Data Sheet (December, 2001).pdf|Mobile AMD Duron Processor Model 7 Data Sheet]]; Publication # 24068; Rev: F; Issue Date: December 2001.

== See also ==
* {{amd|Duron}}
* {{intel|Celeron}}
base frequency	950 MHz (0.95 GHz, 950,000 kHz) +
bus rate	200 MT/s (0.2 GT/s, 200,000 kT/s) +
bus speed	100 MHz (0.1 GHz, 100,000 kHz) +
bus type	FSB +
clock multiplier	9.5 +
core count	1 +
core family	6 +
core model	7 +
core name	Morgan +
core stepping	0 +
core voltage	1.45 V (14.5 dV, 145 cV, 1,450 mV) +
core voltage tolerance	0.1 V +
cpuid	670 +
designer	AMD +
die area	105.68 mm² (0.164 in², 1.057 cm², 105,680,000 µm²) +
family	Duron +
first announced	November 12, 2001 +
first launched	November 12, 2001 +
full page name	amd/duron/dhm0950aqs1b +
has feature	Halt State + and Sleep State +
has locked clock multiplier	true +
instance of	microprocessor +
io voltage	2.5 V (25 dV, 250 cV, 2,500 mV) +
io voltage tolerance	0.25 V +
l1d$ description	2-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	2-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	16-way set associative +
l2$ size	0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldate	November 12, 2001 +
manufacturer	AMD +
market segment	Mobile +
max case temperature	368.15 K (95 °C, 203 °F, 662.67 °R) +
max cpu count	1 +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max storage temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
microarchitecture	K7 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	233.15 K (-40 °C, -40 °F, 419.67 °R) +
model number	Duron 950 +
name	Duron 950 +
part number	DHM0950AQS1B +
process	180 nm (0.18 μm, 1.8e-4 mm) +
series	Duron Mobile +
smp max ways	1 +
tdp	25 W (25,000 mW, 0.0335 hp, 0.025 kW) +
technology	CMOS +
thread count	1 +
transistor count	25,180,000 +
word size	32 bit (4 octets, 8 nibbles) +