From WikiChip
Editing amd/duron/d650ast1b

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{amd title|Duron 650 (Spitfire)}}
 
{{amd title|Duron 650 (Spitfire)}}
{{chip
+
{{mpu
 
| name                = Duron 650
 
| name                = Duron 650
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = Duron 650
 
| model number        = Duron 650
 
| part number        = D650AST1B
 
| part number        = D650AST1B
 +
| part number 1      =
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
| part number 4      =
 
 
| market              = Desktop
 
| market              = Desktop
 
| first announced    = June 5, 2000
 
| first announced    = June 5, 2000
Line 45: Line 45:
 
| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
| max memory          = 4 GiB
+
| max memory          = 4 GB
 
 
  
 +
| electrical          = Yes
 
| power              =  
 
| power              =  
 
| v core              = 1.5 V
 
| v core              = 1.5 V
Line 79: Line 79:
 
| socket 0 type      = PGA-462
 
| socket 0 type      = PGA-462
 
}}
 
}}
'''Duron 650''' based on the {{amd|Spitfire|l=core}} core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W.
+
'''Duron 650''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W.
  
 
== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{cache info
 
{{cache info
|l1i cache=64 KiB
+
|l1i cache=64 KB
|l1i break=1x64 KiB
+
|l1i break=1x64 KB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=64 KiB
+
|l1d cache=64 KB
|l1d break=1x64 KiB
+
|l1d break=1x64 KB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
 
|l1d extra=
 
|l1d extra=
|l2 cache=64 KiB
+
|l2 cache=64 KB
|l2 break=1x64 KiB
+
|l2 break=1x64 KB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=
 
|l2 extra=
Line 106: Line 106:
  
 
== Features ==  
 
== Features ==  
{{x86 features
+
{{mpu features
 
| em64t      =  
 
| em64t      =  
 
| nx          =  
 
| nx          =  
Line 145: Line 145:
 
* [[has feature::Halt State]]
 
* [[has feature::Halt State]]
 
* [[has feature::Sleep State]]
 
* [[has feature::Sleep State]]
 
== Documents ==
 
=== DataSheet ===
 
* [[:File:AMD Duron Processor Model 3 Data Sheet (June, 2001).pdf|AMD Duron Processor Model 3 Data Sheet]]; Publication # 23802; Rev: I; Issue Date: June 2001.
 
=== Other ===
 
* [[:File:AMD Duron Processor Model 3 Revision Guide (October, 2003).pdf|AMD Duron Processor Model 3 Revision Guide]]; Publication # 23865; Rev: K; Issue Date: October 2003.
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
base frequency650 MHz (0.65 GHz, 650,000 kHz) +
bus rate200 MT/s (0.2 GT/s, 200,000 kT/s) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
bus typeFSB +
clock multiplier6.5 +
core count1 +
core family6 +
core model3 +
core nameSpitfire +
core stepping0 +
core voltage1.5 V (15 dV, 150 cV, 1,500 mV) +
core voltage tolerance0.1 V +
cpuid630 +
designerAMD +
die area100 mm² (0.155 in², 1 cm², 100,000,000 µm²) +
familyDuron +
first announcedJune 5, 2000 +
first launchedJune 19, 2000 +
full page nameamd/duron/d650ast1b +
has featureHalt State + and Sleep State +
has locked clock multipliertrue +
instance ofmicroprocessor +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldateJune 19, 2000 +
manufacturerAMD +
market segmentDesktop +
max case temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max storage temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
microarchitectureK7 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberDuron 650 +
nameDuron 650 +
part numberD650AST1B +
process180 nm (0.18 μm, 1.8e-4 mm) +
seriesDuron Desktop +
smp max ways1 +
tdp24.3 W (24,300 mW, 0.0326 hp, 0.0243 kW) +
technologyCMOS +
thread count1 +
transistor count25,000,000 +
word size32 bit (4 octets, 8 nibbles) +