From WikiChip
Editing amd/cores/vermeer

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
 
{{amd title|Vermeer|core}}
 
{{amd title|Vermeer|core}}
 
{{core
 
{{core
 +
|no image=Yes
 
|name=Vermeer
 
|name=Vermeer
|no image=Yes
 
 
|developer=AMD
 
|developer=AMD
 
|manufacturer=TSMC
 
|manufacturer=TSMC
Line 15: Line 14:
 
|proc=7 nm
 
|proc=7 nm
 
|tech=CMOS
 
|tech=CMOS
|clock min=3,000 MHz
+
|package module 1={{packages/amd/socket am4}}
|clock max=3,800 MHz
 
|package name 1=amd,socket_am4
 
 
|predecessor=Matisse
 
|predecessor=Matisse
 
|predecessor link=amd/cores/matisse
 
|predecessor link=amd/cores/matisse
|successor=Raphael
 
|successor link=amd/cores/raphael
 
|contemporary=Vermeer-X
 
|contemporary link=amd/cores/vermeer
 
 
}}
 
}}
 
'''Vermeer''' is codename for [[AMD]]'s mainstream through high-end desktop (HEDT) microprocessor line based on the {{amd|Zen 3|l=arch}} microarchitecture serving as a successor to {{\\|Matisse}}. Vermeer processors are fabricated on [[TSMC]] [[7 nm process]].
 
'''Vermeer''' is codename for [[AMD]]'s mainstream through high-end desktop (HEDT) microprocessor line based on the {{amd|Zen 3|l=arch}} microarchitecture serving as a successor to {{\\|Matisse}}. Vermeer processors are fabricated on [[TSMC]] [[7 nm process]].
Line 31: Line 24:
 
== Overview ==
 
== Overview ==
 
Vermeer processors are the successor to {{\\|Matisse}}, fabricated on a [[7 nm process]] based on the {{amd|Zen 3|l=arch}} microarchitecture. Those processors are a complete [[system on a chip]] with both the [[northbridge]] and [[southbridge]] on-chip. Matisse chips offer 16 PCIe Gen 4.0 lanes (generally for the GPU) along with four additional x4 PCIe lanes for SATA.
 
Vermeer processors are the successor to {{\\|Matisse}}, fabricated on a [[7 nm process]] based on the {{amd|Zen 3|l=arch}} microarchitecture. Those processors are a complete [[system on a chip]] with both the [[northbridge]] and [[southbridge]] on-chip. Matisse chips offer 16 PCIe Gen 4.0 lanes (generally for the GPU) along with four additional x4 PCIe lanes for SATA.
 
=== Memory Interface ===
 
"Vermeer" processors implement two [[wikipedia:DDR4 SDRAM|DDR4]] memory controllers designed for data rates up to 3200 MT/s. Higher frequencies are possible using memory rated for speeds outside the DDR4 standard, however damages caused by overclocking are not covered under warranty. The controllers support up to 2 DIMMs per channel, namely single or dual rank UDIMMs built with x4 or x8 DDR4 devices. ECC is supported<ref>[https://community.amd.com/t5/processors/ryzen-5000-series-ecc-support/td-p/428780 "Ryzen 5000 series ECC support?"]. AMD Community Forum. Retrieved May 2021.</ref> but the feature is generally only validated for "PRO" models and requires an ECC-capable motherboard, BIOS, and operating system. All motherboards should accept ECC DIMMs, this is not proof that error correction was enabled. The maximum total memory capacity is 128 GiB using four UDIMMs of 32 GiB capacity.
 
 
{| class="wikitable" style="display: inline-table; text-align: center;"
 
! colspan="5" | Memory speed based on DIMM population
 
|-
 
! colspan="2" | Channel A || colspan="2" | Channel B || rowspan="2" | Max. Data Rate<br/>(MT/s)
 
|-
 
! DIMM0 || DIMM1 || DIMM0 || DIMM1
 
|-
 
| - || SR || - || - || 3200
 
|-
 
| - || DR || - || - || 3200
 
|-
 
| - || SR || - || SR || 3200
 
|-
 
| - || DR || - || DR || 3200
 
|-
 
| SR || SR || SR || SR || 2933
 
|-
 
| SR/DR || DR || SR/DR || DR || 2667
 
|-
 
| SR/DR || SR/DR || SR/DR || SR/DR || 2667
 
|}
 
DIMM0 on Channel A is the module closest to the CPU. DIMM0 sockets are not present on motherboards with only two memory slots.
 
 
Please consult the motherboard manual and memory compatibility list provided by the manufacturer for memory installation advice.
 
  
 
=== Common Features ===
 
=== Common Features ===
Line 182: Line 147:
 
{{clear}}
 
{{clear}}
  
== References ==
 
{{reflist}}
 
  
 
== See also ==
 
== See also ==
 
{{amd zen 3 core see also}}
 
{{amd zen 3 core see also}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Facts about "Vermeer - Cores - AMD"
designerAMD +
first announcedOctober 8, 2020 +
first launchedNovember 5, 2020 +
instance ofcore +
isax86-64 +
isa familyx86 +
manufacturerTSMC + and Globalfoundries +
microarchitectureZen 3 +
nameVermeer +
packageOPGA-1331 +
process7 nm (0.007 μm, 7.0e-6 mm) +
socketSocket AM4 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +