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{{amd title|Naples|core}} | {{amd title|Naples|core}} | ||
{{core | {{core | ||
− | |name=Naples | + | | name = Naples |
− | |image=amd naples | + | | image = amd naples.png |
− | | | + | | image size = |
− | | | + | | image 2 = |
− | |developer=AMD | + | | image 2 size = |
− | |manufacturer=GlobalFoundries | + | | developer = AMD |
− | |first announced=March 7, 2017 | + | | manufacturer = GlobalFoundries |
− | |first launched= | + | | first announced = March 7, 2017 |
− | |isa=x86-64 | + | | first launched = |
− | |microarch=Zen | + | | isa = x86-64 |
− | |word=64 bit | + | | microarch = Zen |
− | |proc=14 nm | + | | word = 64 bit |
− | |tech=CMOS | + | | proc = 14 nm |
− | |clock min= | + | | tech = CMOS |
− | |clock max= | + | | clock min = |
− | |package | + | | clock max = |
− | |successor= | + | | package = LGA-4094 |
− | |successor link=amd/cores/ | + | | socket = Socket SP3 |
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = | ||
+ | | predecessor link = | ||
+ | | successor = Starship | ||
+ | | successor link = amd/cores/starship | ||
}} | }} | ||
− | '''Naples''' is | + | '''Naples''' is the name of the cores for [[AMD]]'s highest-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen|l=arch}} microarchitecture. Naples processors support up [[32 cores]] and are fabricated on GlobalFoundries' [[14 nm process]]. |
+ | |||
+ | Naples processors are set to be introduced in the 2nd quarter of 2017. | ||
== Overview == | == Overview == | ||
[[File:amd naples 2 sock.jpg|right|thumb]] | [[File:amd naples 2 sock.jpg|right|thumb]] | ||
− | AMD Naples [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen|l=arch}} microarchitecture. Naples SoCs support both single and 2-way multiprocessing with up to a maximum of 32 cores (and 64 threads) per processor for a total of up to 64 cores (and 128 threads) for a 2-way MP system. Those SoCs sports 128 PCIe lanes each, however | + | AMD Naples [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen|l=arch}} microarchitecture. Naples SoCs support both single and 2-way multiprocessing with up to a maximum of 32 cores (and 64 threads) per processor for a total of up to 64 cores (and 128 threads) for a 2-way MP system. Those SoCs sports 128 PCIe lanes each, however half of them are lost when in 2-way MP (leaving the system with the same overall lanes count as a single socket solution). Communication between the two chips is done via AMD's {{amd|Infinity Fabric}} protocol over the 64 [[PCIe]] reserved lanes. |
=== Common Features === | === Common Features === | ||
All Naples processors have the following: | All Naples processors have the following: | ||
− | |||
* Octa-channel Memory | * Octa-channel Memory | ||
− | ** Up to DDR4- | + | ** Up to DDR4-2400 ECC |
** Up to 2 [[TiB]] (4 TiB in 2MP) | ** Up to 2 [[TiB]] (4 TiB in 2MP) | ||
* Up to 32 cores / 64 threads | * Up to 32 cores / 64 threads | ||
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
− | == | + | |
+ | |||
+ | == Summit Ridge Processors == | ||
<!-- NOTE: | <!-- NOTE: | ||
This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
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created and tagged accordingly. | created and tagged accordingly. | ||
− | Missing a chip? please dump its name here: | + | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips |
--> | --> | ||
+ | |||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc12 tc13"> |
− | + | <tr class="comptable-header"><th> </th><th colspan="12">List of Naples Processors</th></tr> | |
− | {{comp table header|cols | + | <tr class="comptable-header"><th> </th><th colspan="10">Processor</th><th colspan="2">Features</th></tr> |
− | {{#ask: [[Category:microprocessor models by amd]] [[core name::Naples]] | + | {{comp table header 1|cols=Family, Price, Process, Launched, C, T, Freq, Turbo, TDP, Max Mem, AMD-V, XFR}} |
+ | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[core name::Naples]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?microprocessor family | |?microprocessor family | ||
|?release price | |?release price | ||
+ | |?process | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
− | |||
− | |||
− | |||
|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
+ | |?tdp | ||
+ | |?max memory#GiB | ||
+ | |?has amd amd-vi technology | ||
+ | |?has amd extended frequency range | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=14:13 |
|mainlabel=- | |mainlabel=- | ||
− | |||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Naples]]}} | + | <tr><td> </td><td colspan="20">'''There are currently no known Naples processors'''</td></tr> |
+ | {{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[core name::Naples]]}} | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
== See also == | == See also == | ||
− | {{amd | + | * {{amd|Zen|l=arch}} |
+ | ** {{amd|Summit Ridge|l=core}} | ||
* {{intel|Skylake|l=arch}} | * {{intel|Skylake|l=arch}} | ||
** {{intel|Skylake SP|l=core}} | ** {{intel|Skylake SP|l=core}} |
Facts about "Naples - Cores - AMD"
back image | + |
designer | AMD + |
first announced | March 7, 2017 + |
first launched | June 20, 2017 + |
instance of | core + |
isa | x86-64 + |
main image | + |
main image caption | Package, front + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen + |
name | Naples + |
package | FCLGA-4094 + and SP3 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-4094 + and SP3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |