Editing amd/cores/genoa

{{amd title|Genoa|core}}
{{core
|name=Genoa
|no image=Yes
|developer=AMD
|manufacturer=TSMC
|isa=x86-64
|microarch=Zen 4
|word=64 bit
|proc=5 nm
|tech=CMOS
|predecessor=Milan
|predecessor link=amd/cores/milan
}}
[[File:amd epyc roadmap 2021-01.png|thumb|right]]
'''Genoa''' is the codename of [[AMD]]'s high-performance enterprise-level server microprocessors based on the {{amd|Zen 4|l=arch}} microarchitecture which will succeed the {{amd|EPYC#7003 Series (Zen 3)|EPYC 7003}} "{{\\|Milan}}" series.

AMD roadmaps show the CPU cores of these processors will be fabricated on a TSMC [[5 nm process]]. 

"Genoa" processors will power the exaflop supercomputer El Capitan with delivery anticipated in early 2023. They will support next generation memory and I/O subsystems and utilize the third generation of AMD's [[Infinity Fabric|Infinity Architecture]].<ref>[https://www.amd.com/en/products/exascale-era "Powering the Exascale Era"], AMD.com, retrieved April 2021.</ref><ref>[https://www.hpe.com/us/en/newsroom/press-release/2020/03/hpe-and-amd-power-complex-scientific-discovery-in-worlds-fastest-supercomputer-for-us-department-of-energys-doe-national-nuclear-security-administration-nnsa.html "HPE and AMD power complex scientific discovery in world’s fastest supercomputer for U.S. Department of Energy’s (DOE) National Nuclear Security Administration (NNSA)"], HPE.com, retrieved April 2021.</ref>

{{future information}}

Leaked information suggests "Genoa" processors, branded EPYC 7004 series, will be available in a 6096-contact [[land grid array]] package for Socket SP5 with [[TDP]] up to 320 Watt and a configurable TDP-up reaching 400 Watt. They will support 12 channels of [[DDR5]]-5200 memory and 128 [[PCIe]] Gen 5 lanes per socket, up to 160 lanes total on 2P systems as prior generations. "Genoa" processors are expected to implement up to 96 cores with 2-way SMT i.e. 192 threads per socket.<ref>@ExecuFix (February 28, 2021), [https://twitter.com/ExecuFix/status/1365981401808580614 "Genoa"] (Tweet) - via [https://en.wikipedia.org/wiki/Twitter Twitter].</ref> 

{{clear}}

== References ==
<references/>
@@ Line 5: / Line 5: @@
 |developer=AMD
 |manufacturer=TSMC
-|first announced=
-|first launched=November 10, 2022
 |isa=x86-64
 |microarch=Zen 4
 |word=64 bit
 |proc=5 nm
-|proc 2=6 nm
 |tech=CMOS
-|package name 1=amd,socket_sp5
 |predecessor=Milan
 |predecessor link=amd/cores/milan
-|successor=
-|successor link=
 }}
-'''Genoa''' is the codename of [[AMD]]'s {{amd|EPYC#9004 Series (Zen 4)|EPYC 9004 series}} of high-performance microprocessors based on the {{amd|Zen 4|l=arch}} microarchitecture for single- and dual-socket server platforms. Launched in November 2022 it succeeded the third generation of EPYC processors, the {{amd|EPYC#7003 Series (Zen 3)|EPYC 7003}} "{{\\|Milan}}" series.<ref name="pr20221110">[https://ir.amd.com/news-events/press-releases/detail/1100/offering-unmatched-performance-leadership-energy "Offering Unmatched Performance, Leadership Energy Efficiency and Next-Generation Architecture, AMD Brings 4th Gen AMD EPYC™ Processors to The Modern Data Center"] (Press release). AMD.com. November 10, 2022. Retrieved February 2022.</ref>
+[[File:amd epyc roadmap 2021-01.png|thumb|right]]
+'''Genoa''' is the codename of [[AMD]]'s high-performance enterprise-level server microprocessors based on the {{amd|Zen 4|l=arch}} microarchitecture which will succeed the {{amd|EPYC#7003 Series (Zen 3)|EPYC 7003}} "{{\\|Milan}}" series.
-EPYC 9004 processors identify as members of {{amd|CPUID#Family 25 (19h)|AMD CPU Family 19h, Model 11h}} (engineering samples as Model 10h).
+AMD roadmaps show the CPU cores of these processors will be fabricated on a TSMC [[5 nm process]].
-== Overview ==
+"Genoa" processors will power the exaflop supercomputer El Capitan with delivery anticipated in early 2023. They will support next generation memory and I/O subsystems and utilize the third generation of AMD's [[Infinity Fabric|Infinity Architecture]].<ref>[https://www.amd.com/en/products/exascale-era "Powering the Exascale Era"], AMD.com, retrieved April 2021.</ref><ref>[https://www.hpe.com/us/en/newsroom/press-release/2020/03/hpe-and-amd-power-complex-scientific-discovery-in-worlds-fastest-supercomputer-for-us-department-of-energys-doe-national-nuclear-security-administration-nnsa.html "HPE and AMD power complex scientific discovery in world’s fastest supercomputer for U.S. Department of Energy’s (DOE) National Nuclear Security Administration (NNSA)"], HPE.com, retrieved April 2021.</ref>
-{{empty section}}
-=== Memory Interface ===
+{{future information}}
-The "Genoa" I/O die integrates 12 {{wp|DDR5 SDRAM|DDR5}} memory controllers and interfaces, three per I/O die quadrant, which support raw data rates up to 4800&nbsp;MT/s. Up to 2 DIMMs per channel are supported. Each channel has two independent 40-bit (32 data, 8 ECC) DDR5 subchannels. The memory controllers support {{wp|ECC memory}} (80b x4, 80b x8, and 72b x4 ECC, i.e. EC4 and EC8 DIMMs) and DDR5 DRAMs with 16/24/32 Gb density on the following DIMM types:
-* {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}} built with x4 and x8 DDR5 devices (1Rx4 16/32/48 GiB, 1Rx8 16/24 GiB, 2Rx4 64/80/96 GiB, 2Rx8 32/40/48 GiB)
+Leaked information suggests "Genoa" processors, branded EPYC 7004 series, will be available in a 6096-contact [[land grid array]] package for Socket SP5 with [[TDP]] up to 320 Watt and a configurable TDP-up reaching 400 Watt. They will support 12 channels of [[DDR5]]-5200 memory and 128 [[PCIe]] Gen 5 lanes per socket, up to 160 lanes total on 2P systems as prior generations. "Genoa" processors are expected to implement up to 96 cores with 2-way SMT i.e. 192 threads per socket.<ref>@ExecuFix (February 28, 2021), [https://twitter.com/ExecuFix/status/1365981401808580614 "Genoa"] (Tweet) - via [https://en.wikipedia.org/wiki/Twitter Twitter].</ref>
-* 4R/8R {{abbr|LRDIMM}} ({{abbr|2S2R|<nowiki>4 Rank = Dual Rank × 2 dies stacked</nowiki>}}, 2S4R)
-* 4R/8R/16R {{abbr|3DS DIMM}} built with x4 devices (2S2Rx4 128/192 GiB, 2S4Rx4 256/384 GiB, 2S8Rx4 512&nbsp;GiB)
-{{abbr|UDIMM}}, {{abbr|NVDIMM-N}}, {{abbr|NVDIMM-P}} types are not supported.
-The maximum total memory capacity is 6&nbsp;TiB per socket using 3DS DIMMs of e.g. 12 × 512&nbsp;GiB capacity.
-=== Input/Output Interfaces ===
-The "Genoa" I/O die integrates eight 16-lane {{wp|PCI Express|PCIe}} Gen 5 (32&nbsp;GT/s) controllers and interfaces. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links, e.g. 1x8 + 1x4 + 4x1. Each controller supports up to nine PCIe links, or up to eight if any lane is is configured as SATA link, and per link lane reversal which can simplify signal routing on the motherboard.
-Two supplementary I/O interfaces support the PCIe Gen 3 (8&nbsp;GT/s) protocol. Each of these interfaces has four lanes configurable x4, x2, x1 and supports up to four links.
-On dual-socket systems four, or optionally three depending on bandwidth requirements, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these {{abbr|xGMI}} links is also 32&nbsp;GT/s. A {{abbr|WAFL}} link occupying two lanes on one of the supplementary interfaces connects the Control Fabrics of each processor, i.e. the {{abbr|PSP}}, {{abbr|SMU}}s and other IPs, primarily for temperature monitoring, power and frequency control.
-In summary on 1P systems up to 128 PCIe Gen 5 and 8 PCIe Gen 3 lanes are available for I/O. On 2P systems up to 64 or 80 PCIe Gen 5 and 6 PCIe Gen 3 lanes per socket.
-Up to four of the x16 interfaces can be configured as cache-coherent {{wp|Compute Express Link|Compute Express Link}}. "Genoa" supports version 1.1 of the protocol, specifically accelerators without local memory such as a {{abbr|NIC}} using the CXL.io and CXL.cache protocols, and memory expanders using the CXL.io and CXL.memory protocols. One accelerator per interface can be attached with a 1x16 or 1x8 link, or up to four memory expanders with 1x16, 2x8, or 4x4 links. Unused lanes are available for PCIe and configurable 1x8, 2x4, or 3x4.
-The lanes on two x16 interfaces can be configured as SATA Gen 3 links, unused lanes are available for PCIe. On 1P systems up to 32 SATA ports total are available, on 2P systems 16 ports per socket as one of the interfaces is reserved for xGMI duty.
-The processors integrate a controller hub with four USB 3.2 Gen 1×1 (5&nbsp;Gb/s) ports (the I/O die actually implements USB 3.2 Gen 2×1<ref name="AMD-55901-11B1-*">{{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 19h Models 11h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55901_0.25.zip|publ=AMD|pid=55901|rev=0.25|date=2022-11-10}}</ref> which may be available on future {{amd|Ryzen Threadripper}} processors) and several low-speed interfaces listed below.
-For link configuration details see {{amd|Socket SP5|l=package}}.
-=== Feature Summary ===
-* 16 to 96 {{amd|Zen 4|l=arch}} [[x86]] CPU cores with 2-way [[SMT]]
-** Op cache holding up to 6,750 Ops, 2 × 32&nbsp;KiB L1, and 1&nbsp;MiB L2 cache per core
-** x86 extensions ('''new'''): {{x86|ABM}}, {{x86|ADX}}, {{x86|AES}}, {{x86|AVX}}, {{x86|AVX2}}, '''{{x86|AVX512F}}''', '''{{x86|AVX512BW}}''', '''{{x86|AVX512CD}}''', '''{{x86|AVX512DQ}}''', '''{{x86|AVX512VL}}''', '''{{x86|AVX512_BF16}}''', '''{{x86|AVX512_BITALG}}''', '''{{x86|AVX512_IFMA}}''', '''{{x86|AVX512_VBMI}}''', '''{{x86|AVX512_VBMI2}}''', '''{{x86|AVX512_VNNI}}''', '''{{x86|AVX512_VPOPCNTDQ}}''', {{x86|BMI1}}, {{x86|BMI2}}, {{x86|CLFLUSH}}, {{x86|CLFLUSHOPT}}, {{x86|CLWB}}, {{x86|CLZERO}}, {{x86|CMOV}}, {{x86|CMPXCHG8B}}, {{x86|CMPXCHG16B}}, {{x86|EMMX}}, {{x86|F16C}}, {{x86|FMA3}}, {{x86|FPU}}, {{x86|FSGSBASE}}, {{x86|FXSR}}, '''{{x86|GFNI}}''', {{x86|INVLPGB}}, {{x86|INVPCID}}, {{x86|LahfSahf}}, {{x86|MCOMMIT}}, {{x86|MMX}}, {{x86|MONITOR}}, {{x86|MONITORX}}, {{x86|MOVBE}}, {{x86|MSR}}, {{x86|PCLMULQDQ}}, {{x86|PKU}}, {{x86|POPCNT}}, {{x86|PREFETCH}}, {{x86|RDPID}}, {{x86|RDPRU}}, {{x86|RDRAND}}, {{x86|RDTSCP}}, {{x86|RDSEED}}, {{x86|SHA}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4A}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|SysCallSysRet}}, {{x86|SysEnterSysExit}}, {{x86|TSC}}, {{x86|VAES}}, {{x86|VPCLMULQDQ}}, {{x86|WBNOINVD}}, {{x86|XSAVE}}, {{x86|XSAVEC}}, {{x86|XSAVEOPT}}
-** Security extensions: {{x86|CET|CET_SS}}, {{x86|GMET}}, {{x86|NX}}, {{x86|SME|SEV}}, {{x86|SME|SEV-ES}}, {{x86|SME|SEV-SNP}}, {{x86|SMAP}}, {{x86|SME|SME/TSME}}, {{x86|SMEP}}, {{x86|UMIP}}
-** Speculation control: {{x86|IBPB}}, {{x86|IBRS}}, {{x86|PSFD}}, {{x86|SSBD}}, {{x86|STIBP}}
-* 32&nbsp;MiB L3 cache per Core Complex (8 CPU cores), 64 to 384 MiB total
-* 12 × 80-bit DDR5 SDRAM interface up to 2400&nbsp;MHz, PC5-38400 (DDR5-4800), 460.8&nbsp;GB/s
-** Two independent 40-bit (32 data, 8 ECC) DDR5 subchannels per channel
-** Up to 2 DIMMs per channel, 24 total
-** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, 4R/8R/16R {{abbr|3DS DIMM}}
-** ECC supported (x4, x8, x16, chipkill)<!--AMD-55901-0.97 Sec 3.7-->
-** DRAM bus parity and write data {{abbr|CRC}} options<!--ibid-->
-** Up to 6&nbsp;TiB total
-* Eight 16-lane PCIe Gen 5 (32&nbsp;GT/s) controllers
-** Configurable x16, x8, x4, x2, x1
-** Up to 9 links per controller
-** {{abbr|xGMI}} protocol supported on 4 × 16 lanes, 2P systems only
-** {{abbr|CXL}} 1.1 protocol supported on 4 × 16 lanes
-** SATA Gen 3 protocol supported on 2 × 16 lanes
-* Two 4-lane PCIe Gen 3 (8&nbsp;GT/s) controllers
-** {{abbr|WAFL}} protocol supported on two lanes, 2P systems only
-* Four USB 3.2 Gen 1×1 (5&nbsp;Gb/s) ports
-* Low speed interfaces (some are alternative functions on shared pins):
-** 3 × 2-wire or 1 × 4-wire + 1 × 2-wire {{abbr|UART}}
-** 2 × 1/2/4-bit {{abbr|SPI/eSPI}}
-** 4 × {{abbr|I<sup>3</sup>C}}
-** 6 × {{abbr|I<sup>2</sup>C}}
-** 2 × {{abbr|SMBus}}
-** 4 × {{abbr|SGPIO}}
-** 2 × SATA {{abbr|DevSlp}}
-** 76 × {{abbr|GPIO}}
-** Sideband Interface a.k.a. {{abbr|APML}}-I3C ({{abbr|SB-RMI}}, {{abbr|SB-TSI}}) for health monitoring by a {{abbr|BMC}}
-** 2 × Serial VID Interface (SVI3) for voltage control
-** {{abbr|JTAG}}
-* {{amd|secure processor|AMD Secure Processor}}, [[Secure Boot]], Hardware root-of-trust
-* {{abbr|TDP}} range 200 to 400 Watt, configurable
-=== Naming Scheme ===
-{{chip identification
-| title     =
-| parts     = 7
-| ex 1      = EPYC
-| ex 2      = &nbsp;
-| ex 3      = 9
-| ex 4      = 6
-| ex 5      = 5
-| ex 6      = 4
-| ex 7      = P
-| desc 1    = <table style="text-align:left"><th colspan="2">Product Family</th>
-<tr><td>EPYC</td></tr>
-</table>
-| desc 3    = <table style="text-align:left"><th colspan="2">Product Series</th>
-<tr><th>9xxx</th><td>High-performance server CPU/{{abbr|SoC}}</td></tr>
-</table>
-| desc 4    = <table style="text-align:left"><th colspan="2">Product Model</th>
-<tr><th>0</th><td>8 cores</td></tr>
-<tr><th>1</th><td>16 cores</td></tr>
-<tr><th>2</th><td>24 cores</td></tr>
-<tr><th>3</th><td>32 cores</td></tr>
-<tr><th>4</th><td>48 cores</td></tr>
-<tr><th>5</th><td>64 cores</td></tr>
-<tr><th>6</th><td>84-96 cores</td></tr>
-</table>
-| desc 5    = '''Performance Level''', higher number is better
-| desc 6    = <table style="text-align:left"><th colspan="2">Generation</th>
-<tr><th>4</th><td>Fourth generation, 9004 "Genoa" series, {{amd|Zen 4|l=arch}} microarchitecture</td></tr>
-</table>
-| desc 7    = <table style="text-align:left"><th colspan="2">Feature Modifier</th>
-<tr><th>(none)</th><td>1P, 2P</td></tr>
-<tr><th>P</th><td>1P (single socket) only</td></tr>
-<tr><th>F</th><td>Frequency optimized</td></tr>
-</table>
-}}
-Source: <ref name="AMD-58015-*">{{cite techdoc|title=AMD EPYC™ 9004 Series Architecture Overview|url=https://www.amd.com/system/files/documents/58015-epyc-9004-tg-architecture-overview.pdf|publ=AMD|pid=58015|rev=1.1|date=2022-12}}</ref>
-== Genoa Processors ==
-<!-- NOTE:
-    This table is generated automatically from the data in the actual articles.
-    If a microprocessor is missing from the list, an appropriate article for it needs to be
-    created and tagged accordingly.
-    Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
--->
-{{comp table start}}
-<table class="comptable sortable">
-{{comp table header|main|15:List of Genoa Processors}}
-{{comp table header|cols|{{abbr|C|Cores}}|{{abbr|T|Threads}}|L2|L3|Frequ.|Turbo|Turbo 1C|Memory|{{abbr|cTDP}}↓|{{abbr|TDP}}|cTDP↑|Launched|Price 1k|{{abbr|OPN}}}}
-{{comp table header|lsep|15:[[Uniprocessors]]}}
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] [[max cpu count::1]]
-|?full page name
-|?name
-|?core count
-|?thread count
-|?l2$ size
-|?l3$ size
-|?base frequency#GHz
-|?turbo frequency#GHz
-|?turbo frequency (1 core)#GHz
-|?supported memory type
-|?tdp down |?tdp |?tdp up
-|?first launched
-|?release price
-|?part number
-|sort=model number
-|format=template
-|template=proc table 3
-|userparam=16
-|mainlabel=-
-|valuesep=,<br/>
-}}
-{{comp table header|lsep|15:[[Multiprocessors]] (dual-socket)}}
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] [[max cpu count::>>1]]
-|?full page name
-|?name
-|?core count
-|?thread count
-|?l2$ size
-|?l3$ size
-|?base frequency#GHz
-|?turbo frequency#GHz
-|?turbo frequency (1 core)#GHz
-|?supported memory type
-|?tdp down |?tdp |?tdp up
-|?first launched
-|?release price
-|?part number
-|sort=model number
-|format=template
-|template=proc table 3
-|userparam=16
-|mainlabel=-
-|valuesep=,<br/>
-}}
-{{comp table header|lsep|15:Frequency-optimized SKUs}}
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]] [[part of::Frequency-optimized SKUs]]
-|?full page name
-|?name
-|?core count
-|?thread count
-|?l2$ size
-|?l3$ size
-|?base frequency#GHz
-|?turbo frequency#GHz
-|?turbo frequency (1 core)#GHz
-|?supported memory type
-|?tdp down |?tdp |?tdp up
-|?first launched
-|?release price
-|?part number
-|sort=model number
-|format=template
-|template=proc table 3
-|userparam=16
-|mainlabel=-
-|valuesep=,<br/>
-}}
-{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Genoa]]}}
-</table>
-{{comp table end}}
-=== SKU Comparison ===
-Below are a number of SKU comparison graphs based on their specifications.
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]]
- |?core count
- |?base frequency
- |charttitle=Cores vs. Base Frequency
- |numbersaxislabel=Frequency (MHz)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]]
- |?core count
- |?turbo frequency
- |charttitle=Cores vs. Turbo Frequency
- |numbersaxislabel=Frequency (MHz)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]]
- |?core count
- |?tdp
- |charttitle=Cores vs. TDP
- |numbersaxislabel=TDP (W)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by amd]] [[core name::Genoa]]
- |?turbo frequency
- |?tdp
- |charttitle=Frequency vs. TDP
- |numbersaxislabel=TDP (W)
- |labelaxislabel=Frequency (MHz)
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
 {{clear}}
@@ Line 305: / Line 28: @@
 == References ==
 <references/>
-== See also ==
-{{amd zen 4 core see also}}
designer	AMD +
first launched	November 10, 2022 +
instance of	core +
isa	x86-64 +
manufacturer	TSMC +
microarchitecture	Zen 4 +
name	Genoa +
package	SP5 +
process	5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) +
socket	Socket SP5 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +