From WikiChip
Editing amd/cores/applebred
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 27: | Line 27: | ||
* {{amd|K7|l1=arch}}-based. | * {{amd|K7|l1=arch}}-based. | ||
* [[Die shrink]] from [[180 nm]] to a [[130 nm process]] | * [[Die shrink]] from [[180 nm]] to a [[130 nm process]] | ||
− | * Base frequency of 1.4 GHz - | + | * Base frequency of 1.4 GHz - 18 GHz |
− | |||
* {{x86|MMX}}, {{x86|Extended MMX}}, {{x86|3DNow!}}, {{x86|Extended 3DNow!}}, and {{x86|SSE}} | * {{x86|MMX}}, {{x86|Extended MMX}}, {{x86|3DNow!}}, {{x86|Extended 3DNow!}}, and {{x86|SSE}} | ||
* Cache data hardware prefetcher | * Cache data hardware prefetcher |
Facts about "Applebred - Cores - AMD"
designer | AMD + |
first announced | August 2003 + |
first launched | August 2003 + |
instance of | core + |
isa | IA-32 + |
manufacturer | AMD + |
microarchitecture | K7 + |
name | Applebred + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |