Editing alchemy/au1100-500mbc

{{title|Alchemy Au1100-500MBC}}
{{chip
|name=Alchemy Au1100-500MBC
|no image=Yes
|designer=Alchemy
|model number=Au1100-500MBC
|part number=Au1100-500MBCBA
|part number 2=Au1100-500MBCBC
|part number 3=Au1100-500MBCBD
|part number 4=Au1100-500MBCBE
|part number 5=Au1100-500MBCBF
|prid=0x02030201
|prid 2=0x02030202
|prid 3=0x02030203
|prid 4=0x02030204
|market=Embedded
|first announced=
|first launched=April 8, 2002
|last order=
|last shipment=
|release price (tray)=
|family=Alchemy
|frequency=500 MHz
|isa=MIPS32
|microarch=Au1
|platform=
|chipset=
|core stepping=BA
|core stepping 2=BC
|core stepping 3=BD
|core stepping 4=BE
|core stepping 5=BF
|manufacturer=TSMC
|process=130 nm
|transistors=
|technology=CMOS
|die area=
|word size=32 bit
|core count=1
|max cpus=1
|max memory=192 MiB
|v core=1.22 V
|v io=3.3 V
|tdp=
|tdp typical=400 mW
|tcase min=0 °C
|tcase max=70 °C
|tstorage min=-40 °C
|tstorage max=125 °C
}}
'''Au1100-500MBC''' was a {{arch|32}} ultra low power embedded microprocessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[130&nbsp;nm]] process, this {{abbr|SoC}} operates at a base frequency of up to 500 MHz with a typical {{abbr|TDP}} of 400 mW. It was also available as a Pb-free version {{\\|Au1100-500MBD}}.

== Cache ==
{{main|alchemy/microarchitectures/au1#Memory_Hierarchy|l1=Au1 § Cache}}
{{cache size
|l1 cache=32 KiB
|l1i cache=16 KiB
|l1i break=1 × 16 KiB
|l1i desc=4-way set associative
|l1d cache=16 KiB
|l1d break=1 × 16 KiB
|l1d desc=4-way set associative
|l1d policy=write-back
}}

== Memory controller ==
Au1100 processors integrate two independent memory controllers, a DRAM controller which supports 2.5&nbsp;V / 3.3&nbsp;V SDRAM, {{abbr|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency. 

{{memory controller
|type=SDR-133
|ecc=No
|controllers=1
|channels=1
|max mem=192 MiB
|width=32 bit
|max bandwidth=0.500 GB/s
}}

== Expansions ==
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller
** Two USB host ports and one device port
* One 10/100 Mbit/s Ethernet MAC controller
* Two [[wikipedia:SD card|Secure Digital]]/{{abbr|SDIO}} 1.1 controllers
* Low speed interfaces {{abbr|AC97}}, {{abbr|I2S}}, Fast {{abbr|IrDA}}, 2 × {{abbr|SSI}}, 3 × {{abbr|UART}}, and up to 48 {{abbr|GPIO}}s

== Graphics ==
Au1100 processors integrate an LCD controller which supports panels with a resolution up to 800 × 600 pixels.
* TFT: 1/2/4/8-bit mono, 12/16-bit color (4:4:4/5:6:5 RGB)
* STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
* Frame buffer formats:
** 1/2/4/8-bpp palettized
** 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1 RGBI
* Double buffering
* Hardware swivel (90, 180, 270 degrees) for up to 320 × 240 pixel displays
* Two PWM clocks to control contrast and brightness voltages

== Features ==
* 8-channel DMA engine
* {{abbr|RTC}} and {{abbr|TOY|Time Of Year}} timer
* Two interrupt controllers
* Power management unit
* MIPS EJTAG interface
* Idle Mode, Sleep Mode

== Package ==
* 399-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
* 20 × 20 grid, 0.8&nbsp;mm pitch
* 17&nbsp;mm × 17&nbsp;mm × 1.7&nbsp;mm

== Bibliography ==
* {{cite techdoc|title=Product Brief: AMD Alchemy™ Solutions Au1100™ Processor Family Internet Edge Processor|url=https://web.archive.org/web/20061015225845id_/http://www.razamicroelectronics.com/pub_assets/26330D_Au1100.pdf|publ=AMD|pid=26330|rev=D|date=2003}}
* {{cite techdoc|title=AMD Alchemy™ Au1100™ Processor Data Book|url=https://web.archive.org/web/20061020095828id_/http://www.amd.com:80/files/connectivitysolutions/aufamily/au1100/30362D_au1100_databook.pdf|publ=AMD|pid=30362|rev=D|date=2006-04}}
* {{cite techdoc|title=AMD Alchemy™ Au1100™ Processor Specification Update|file=AMD-27353-E Au1100 Spec Update.pdf|publ=AMD|pid=27353|rev=E|date=2005-06}}
* {{cite techdoc|authors=Bassett, Paul|title=Alchemy Au1x00|url=https://hc14.hotchips.org|publ=Hot Chips 14|date=2002-08-19}}
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	1 +
core stepping	BA +, BC +, BD +, BE + and BF +
core voltage	1.22 V (12.2 dV, 122 cV, 1,220 mV) +
designer	Alchemy +
family	Alchemy +
first launched	April 8, 2002 +
full page name	alchemy/au1100-500mbc +
has ecc memory support	false +
instance of	microprocessor +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	MIPS32 +
l1$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description	4-way set associative +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	4-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
ldate	April 8, 2002 +
manufacturer	TSMC +
market segment	Embedded +
max case temperature	343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count	1 +
max memory	192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth	0.466 GiB/s (476.837 MiB/s, 0.5 GB/s, 500 MB/s, 4.547474e-4 TiB/s, 5.0e-4 TB/s) +
max memory channels	1 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Au1 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	233.15 K (-40 °C, -40 °F, 419.67 °R) +
model number	Au1100-500MBC +
name	Alchemy Au1100-500MBC +
part number	Au1100-500MBCBA +, Au1100-500MBCBC +, Au1100-500MBCBD +, Au1100-500MBCBE + and Au1100-500MBCBF +
process	130 nm (0.13 μm, 1.3e-4 mm) +
smp max ways	1 +
supported memory type	SDR-133 +
tdp (typical)	0.4 W (400 mW, 5.364e-4 hp, 4.0e-4 kW) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +