Editing alchemy/au1000-266mcc

{{title|Alchemy Au1000-266MCC}}
{{chip
|name=Alchemy Au1000-266MCC
|no image=Yes
|designer=Alchemy
|model number=Au1000-266MCC
|part number=Au1000-266MCC
|prid=0x30100
|prid 2=0x30201
|prid 3=0x30202
|prid 4=0x30203
|prid 5=0x30204
|market=Embedded
|first announced=June 13, 2000
|first launched=February 2001
|last order=
|last shipment=
|release price (tray)=
|family=Alchemy
|frequency=266 MHz
|isa=MIPS32
|microarch=Au1
|platform=
|chipset=
|core stepping=DA
|core stepping 2=HA
|core stepping 3=HB
|core stepping 4=HC
|core stepping 5=HD
|manufacturer=TSMC
|process=180 nm
|transistors=
|technology=CMOS
|die area=
|word size=32 bit
|core count=1
|max cpus=1
|max memory=192 MiB
|v core=1.5 V
|v core tolerance=5%
|v io=3.3 V
|tdp=
|tdp typical=300 mW
|tcase min=0 °C
|tcase max=85 °C
|tstorage min=-40 °C
|tstorage max=125 °C
}}
'''Au1000-266MCC''' was a {{arch|32}} ultra low power embedded microprocessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[Alchemy Semiconductor]] and fabricated on a [[TSMC]] [[180&nbsp;nm]] LV process, this {{abbr|SoC}} operates at a base frequency of up to 266 MHz with a typical {{abbr|TDP}} of 300 mW. It was also available with an industrial temperature range as {{\\|Au1000-266MCI}}.

== Cache ==
{{main|alchemy/microarchitectures/au1#Memory_Hierarchy|l1=Au1 § Cache}}
{{cache size
|l1 cache=32 KiB
|l1i cache=16 KiB
|l1i break=1 × 16 KiB
|l1i desc=4-way set associative
|l1d cache=16 KiB
|l1d break=1 × 16 KiB
|l1d desc=4-way set associative
|l1d policy=write-back
}}

== Memory controller ==
Au1000 processors integrate two independent memory controllers, a DRAM controller which supports SDRAM, {{abbr|SMROM}}, and SyncFlash, and a static bus controller which supports SRAM, ROM, Flash memory, {{abbr|PCMCIA}}/CompactFlash devices, and I/O peripherals such as an external LCD controller. SDRAM runs at one half of the frequency of the internal 32-bit System Bus, which runs at up to one half of the CPU core frequency. 

{{memory controller
|type=SDR-133
|ecc=No
|controllers=1
|channels=1
|max mem=192 MiB
|width=32 bit
|max bandwidth=0.266 GB/s
}}

== Expansions ==
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller
** Two USB host ports and one device port
* Two 10/100 Mbit/s Ethernet MAC controllers
* Low speed interfaces {{abbr|AC97}}, {{abbr|I2S}}, Fast {{abbr|IrDA}}, 2 × {{abbr|SSI}}, 4 × {{abbr|UART}}, and up to 32 {{abbr|GPIO}}s

== Graphics ==
This processor has no integrated graphics processing unit.

== Features ==
* 8-channel DMA engine
* {{abbr|RTC}} and {{abbr|TOY|Time Of Year}} timer
* Two interrupt controllers
* Power management unit
* MIPS EJTAG interface
* Idle Mode, Sleep Mode

== Package ==
* 324-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package
* 22 × 22 grid, 1.0&nbsp;mm pitch
* 23&nbsp;mm × 23&nbsp;mm × 1.5&nbsp;mm

== Bibliography ==
* {{cite techdoc|title=Product Brief: The Alchemy Au1000™ Internet Edge Processor|file=Alchemy-Au1000-PB.pdf|publ=Alchemy|date=2000}}
* {{cite techdoc|title=Product Brief: AMD Alchemy™ Solutions Au1000™ Processor Family Internet Edge Processor|url=https://web.archive.org/web/20061015230909id_/http://www.razamicroelectronics.com/pub_assets/26328E_Au1000.pdf|publ=AMD|pid=26328|rev=E|date=2003}}
* {{cite techdoc|title=AMD Alchemy™ Au1000™ Processor Data Book|url=https://web.archive.org/web/20061015230659id_/http://www.razamicroelectronics.com/pub_assets/30360D_au1000_databook.pdf|publ=AMD|pid=30360|rev=D|date=2005-09}}
* {{cite techdoc|title=AMD Alchemy™ Au1000™ Processor Specification Update|file=AMD-27348-E Au1000 Spec Update.pdf|publ=AMD|pid=27348|rev=E|date=2005-06}}
* {{cite techdoc|authors=Hoeppner, Greg|title=Au1000 Internet Edge Processor|file=Au1000 Internet Edge Processor presentation.ppt|publ=Embedded Processor Forum 2000|date=2000-06-13}}
* {{cite techdoc|authors=Plummer, Suzanne|title=The Au1000™ Internet Edge Processor: A High Performance, Low Power SOC|url=https://hc12.hotchips.org|publ=Hot Chips 12|date=2000-08-13}}
* {{cite techdoc|authors=Bassett, Paul|title=Alchemy Au1x00|url=https://hc14.hotchips.org|publ=Hot Chips 14|date=2002-08-19}}
base frequency	266 MHz (0.266 GHz, 266,000 kHz) +
core count	1 +
core stepping	DA +, HA +, HB +, HC + and HD +
core voltage	1.5 V (15 dV, 150 cV, 1,500 mV) +
core voltage tolerance	5% +
designer	Alchemy +
family	Alchemy +
first announced	June 13, 2000 +
first launched	February 2001 +
full page name	alchemy/au1000-266mcc +
has ecc memory support	false +
instance of	microprocessor +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	MIPS32 +
l1$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description	4-way set associative +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	4-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
ldate	February 2001 +
manufacturer	TSMC +
market segment	Embedded +
max case temperature	358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count	1 +
max memory	192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB, 1.831055e-4 TiB) +
max memory bandwidth	0.248 GiB/s (253.677 MiB/s, 0.266 GB/s, 266 MB/s, 2.419256e-4 TiB/s, 2.66e-4 TB/s) +
max memory channels	1 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Au1 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	233.15 K (-40 °C, -40 °F, 419.67 °R) +
model number	Au1000-266MCC +
name	Alchemy Au1000-266MCC +
part number	Au1000-266MCC +
process	180 nm (0.18 μm, 1.8e-4 mm) +
smp max ways	1 +
supported memory type	SDR-133 +
tdp (typical)	0.3 W (300 mW, 4.023e-4 hp, 3.0e-4 kW) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +