Editing alchemy/alchemy

{{title|Alchemy}}
{{ic family
| title             = Alchemy
| developer         = Alchemy
| developer 2       = AMD
| developer 3       = RMI
| manufacturer      = TSMC
| type              = Microprocessor, System on a Chip
| first announced   = June 13, 2000
| arch              = MIPS32
| microarch         = Au1
| word              = 32 bit
| proc              = 180 nm
| proc 2            = 130 nm
| tech              = CMOS
| clock min         = 266 MHz
| clock max         = 1000 MHz
}}

'''Alchemy''' is a family of high performance, ultra low power embedded microprocessors implementing the [[MIPS32]] ISA. They were originally designed by [[Alchemy Semiconductor]] and target communication and media devices, e.g. wireless gateways and access points; VoIP, navigation, and NAS devices; STBs, thin clients, mobile TV and media players, and digital photo frames.

== Overview ==
Alchemy Semiconductor unveiled the Au1000 processor at the Embedded Processor Forum in San Jose, CA, on June 13, 2000, with limited customer sampling in February 2001 and availability in production quantities in Q2 of that year. The Au1500, integrating a PCI controller, was announced one year later at EPF 2001, with customer sampling beginning in December 2001. The Au1100 replaced the PCI interface with an LCD controller and was introduced on April 8, 2002. In February 2002 [[AMD]] acquired Alchemy Semiconductor in order to compete with [[Intel]]'s ARM-based [[XScale]] processors. AMD's Alchemy family gained the new members Au1550 and Au1200 with announcements in February 2004 and January 2005 respectively, as well as the Am1772 wireless chipset consisting of the Am1770 transceiver and Am1771 integrated baseband/MAC chips. In 2006 Intel sold its XScale PXA family to [[Marvell]] while [[Raza Microelectronics]], later renamed RMI Corporation, secured the Alchemy line and some of its designers from AMD. On January 9, 2007 RMI announced the Au1210 and Au1250 with full production in Q2, and in January 2009 the Au13xx models integrating a graphics processor. In October 2009 RMI merged with [[NetLogic Microsystems]] who was in turn acquired by [[Broadcom]] in 2012.

All processors of the Alchemy family use the {{alchemy|Au1|l=arch}} CPU core designed by Alchemy Semiconductor and integrate peripherals licensed from third parties, always including an SDRAM controller, a static bus controller, a DMA controller, two interrupt controllers, two timers {{abbr|RTC}} and {{abbr|TOY|Time Of Year}}, an EJTAG interface compliant with the MIPS specification, and a power management unit. Other peripherals vary with the target market.

The CPU core, the memory controllers, and other high speed peripherals are linked by an internal System Bus (SBUS) which carries a 36-bit physical address, 32-bit data, and a byte mask, running at a configurable ratio of 1/2, 1/3, or 1/4 of the core frequency. Low speed, non-bus master capable peripherals are attached with an ancillary Peripheral Bus (PBUS) running at one half of the SBUS frequency.

For power management the core supports two ''Idle'' modes clock-gating the core. In one of these modes the data cache remains operational, snooping the SBUS to maintain coherency. {{abbr|GPR}}s and CP0 registers are preserved in both modes, the CP0 constant rate timer increments at an unpredictable rate while RTC and TOY are unaffected. ''Sleep'' mode puts the SDRAMs into self-refresh mode and powers down all peripherals except TOY. In ''Hibernate'' mode, on models supporting it, the entire board can be powered down while a battery keeps the TOY counter running.

Au1000 and Au1500 processors were fabricated on a [[TSMC]] [[180&nbsp;nm]] LV logic 1.5V/3.3V 1P6M process, the Au1100 reduced power consumption further with a [[TSMC]] [[130&nbsp;nm]] process. Manufacturing details of later models are unknown. The nominal core voltage is 1.0, 1.2, 1.5, or 1.8&nbsp;V depending on model, the I/O voltage 3.3&nbsp;V.

Each member of the family was available with different core frequency and hence power ratings, different temperature ranges, and earlier models in a Pb-free or standard package. A low profile, fine pitch plastic ball grid array (LF-PBGA) package was used for all models.

== Members ==
=== Au1000 Processors ===
These processors integrate the following peripherals:
* 32-bit SDR-133 SDRAM controller
* 32-bit static bus controller
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller
** Two USB host ports and one device port
* Two 10/100 Mbit/s Ethernet MAC controllers
* Low speed interfaces {{abbr|AC97}}, {{abbr|I2S}}, Fast {{abbr|IrDA}}, 2 × {{abbr|SSI}}, 4 × {{abbr|UART}}, and up to 32 {{abbr|GPIO}}s

The SDRAM controller supports SDRAM, {{abbr|SMROM}}, and SyncFlash. It should be noted that SDRAMs are clocked at one half of the SBUS frequency and therefore one quarter of the core frequency. Accordingly the 266 and 400&nbsp;MHz models are expected to be paired with SDR-66 and SDR-100 DRAMs respectively, and the 500&nbsp;MHz model cannot quite realize the maximum bandwidth of SDR-133 memory. This also applies to the Au1500 and Au1100 processors.

The static bus controller has an interface with 32-bit data and address bus and supports SRAM, ROM, standard Flash memory, page mode Flash/ROM, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller.

The Au1000, Au1500, and Au1100 processors contain an eight-channel DMA controller. Each channel is capable of transferring data between memory and any of the integrated peripherals or between memory and a memory-mapped FIFO through the static bus controller using a GPIO as DMA request. Memory-to-memory transfers are not supported.

Au1000 processors identify with {{mips|PRId register|PRId}} 0x00030101 (Au1 rev. 1, stepping DA) and 0x00030201 to 0x00030204 (Au1 rev. 2, stepping HA to HD). They have a typical TDP between 300 and 900&nbsp;mW. The CPU core runs at 1.5 or 1.8&nbsp;V nominal ±5% and is rated for frequencies between 266 and 500&nbsp;MHz. They shipped in a 23&nbsp;mm × 23&nbsp;mm × 1.5&nbsp;mm, 324-pin LF-PBGA package with 1.0&nbsp;mm ball pitch.

=== Au1500 Processors ===
These processors integrate the following peripherals:
* 32-bit SDR-133 SDRAM controller
* 32-bit static bus controller
* PCI 2.2 controller, 32-bit bus, 33 or 66&nbsp;MHz
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller
** Two USB host ports and one device port
* Two 10/100 Mbit/s Ethernet MAC controllers
* Low speed interfaces {{abbr|AC97}}, 2 × {{abbr|UART}}, and up to 39 {{abbr|GPIO}}s

Au1500 processors identify with PRId 0x01030200 to 0x01030202. They have a typical TDP between 400 and 1200&nbsp;mW. The CPU core runs at 1.5 or 1.8 V nominal ±5% and is rated for frequencies between 333 and 500&nbsp;MHz. They shipped in a 19&nbsp;mm × 19&nbsp;mm × 1.45&nbsp;mm, 424-pin LF-PBGA package with 0.8&nbsp;mm ball pitch.

=== Au1100 Processors ===
These processors integrate the following peripherals:
* 32-bit 2.5V/3.3V SDR-133 SDRAM controller,
* 32-bit static bus controller
* LCD controller
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller
** Two USB host ports and one device port
* One 10/100 Mbit/s Ethernet MAC controller
* Two [[wikipedia:SD card|Secure Digital]]/{{abbr|SDIO}} 1.1 controllers
* Low speed interfaces {{abbr|AC97}}, {{abbr|I2S}}, Fast {{abbr|IrDA}}, 2 × {{abbr|SSI}}, 3 × {{abbr|UART}}, and up to 48 {{abbr|GPIO}}s

The integrated LCD controller supports panels with a resolution up to 800 × 600 pixels.
* TFT: 1/2/4/8-bit mono, 12/16-bit color (4:4:4/5:6:5 RGB)
* STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
* Frame buffer formats:
** 1/2/4/8-bpp palettized
** 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1 RGBI
* Double buffering
* Hardware swivel (90, 180, 270 degrees) for up to 320 × 240 pixel displays
* Two PWM clocks to control contrast and brightness voltages

Au1100 processors identify with PRId 0x02030201 to 0x02030204. They have a typical TDP between 200 and 400&nbsp;mW. The CPU core runs at 1.22&nbsp;V nominal (1.12-1.32&nbsp;V) and is rated for frequencies between 333 and 500&nbsp;MHz. They shipped in a 17 mm × 17&nbsp;mm × 1.7&nbsp;mm, 399-pin LF-PBGA package with 0.8&nbsp;mm ball pitch.

=== Au1550 Security Network Processors ===
These processors integrate the following peripherals:
* 16/32-bit SDR/DDR SDRAM controller
* 32-bit static bus controller
* PCI 2.2 controller, 32-bit bus, 33 or 66&nbsp;MHz
* USB 1.1 ({{abbr|OHCI}}) host controller, USB 1.1 device controller with OTG support
** Two USB host ports and one device port (co-opting a host port in OTG mode)
* Two 10/100 Mbit/s Ethernet MAC controllers
* Four Programmable Serial Controllers supporting the {{abbr|AC97}}, {{abbr|I2S}}, {{abbr|SPI}}, and {{abbr|SMBus}} protocols
* Three {{abbr|UART}}s
* Up to 43 {{abbr|GPIO}}s

* Descriptor-based DMA controller
* SafeNet Security Engine

The SDRAM controller supports 3.3&nbsp;V (standard) and 2.5&nbsp;V (mobile) SDR devices up to SDR-166, and 2.5&nbsp;V DDR devices up to DDR-400. The DRAM to SBUS clock ratio is configurable 1:1 or 1:2, the SBUS to CPU core frequency 1:2, 1:3, or 1:4, so the realizable memory bandwidth again depends on the core frequency and clock ratios. Presumably the 32-bit SBUS has a higher throughput than a 32-bit DRAM bus, but it can certainly not saturate 32-bit ''DDR'' memory running at the same frequency.

The static bus controller has an interface with 32-bit data and 29-bit address bus and supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, and I/O peripherals.

Au1550 and later processors contain a 16-channel DMA controller which operates on linked lists of transfer descriptors in memory. It supports memory to memory, memory to peripheral, peripheral to memory, and peripheral to peripheral transfers, DMA by GPIO request, 36-bit source and destination addresses with no alignment requirement, scatter/gather and stride transfers, compare and branch descriptors for transfers conditional on I/O registers, and various priority policies.

The Security Engine accelerates IP packet encryption/decryption in hardware.
* DES, 3DES, AES, ARC4 encryption algorithms
* MD5, SHA1 hash algorithms
* Supports header/trailer processing, padding, and initialization vector (IV) processing for IPsec packets
* Supports a two-pass hash-then-encrypt implementation of the SSL protocol using either MD5 or SHA1 and 3DES or ARC4 ciphers
* True entropy-based random number generator

Au1550 processors support the Hibernate mode. They identify with PRId 0x0303xxxx. The typical TDP lies between 400 and 600&nbsp;mW. The CPU core runs at 1.2&nbsp;V nominal (1.1-1.3&nbsp;V) and is rated for frequencies between 333 and 500 MHz. They shipped in a 21&nbsp;mm × 21&nbsp;mm × 1.7&nbsp;mm, 483-pin LF-PBGA package with 0.8&nbsp;mm ball pitch.

[https://i.ibb.co/Wxq72zz/00204.jpg Photo] of {{alchemy|Au1500-400MBC}} rev. AD, {{alchemy|Au1550-333MBC}} and {{alchemy|Au1500-333MBD}} rev. AA.

=== Au12xx Processors ===
Members of this series are the '''Au1200 and Au1250 Media Processor''' and the '''Au1210 Navigation Processor''' which integrate the following peripherals:
* 16/32-bit DDR1/DDR2 SDRAM controller
* 16-bit static bus controller
* LCD controller
* Camera Interface Module
* USB 2.0 ({{abbr|EHCI}}) and 1.1 ({{abbr|OHCI}}) host controller, USB 2.0 device controller with OTG support
** One USB host port and one host/device port, each low/fast/high speed capable
* Two [[wikipedia:SD card|Secure Digital]]/{{abbr|SDHC}}/{{abbr|SDIO}}/{{abbr|MMC}} 1.1 controllers
* Two Programmable Serial Controllers supporting the {{abbr|AC97}}, {{abbr|I2S}}, {{abbr|SPI}}, and {{abbr|SMBus}} protocols
* Two {{abbr|UART}}s
* Up to 48 {{abbr|GPIO}}s
* Media Acceleration Engine
* Descriptor-based DMA controller
* AES-128 encryption/decryption in hardware with ECB, CBC, CFB, and OFB block cipher modes (Au1200 and Au1250 only)

The SDRAM controller supports 2.5&nbsp;V DDR devices up to DDR-400 and 1.8&nbsp;V DDR2 devices up to DDR2-533, with the same clock ratios supported by Au1550 processors. It supports two ranks and can address 512 MiB using four 1-Gbit devices. Since the SBUS bandwidth is insufficient for the LCD and MAE peripherals and the SBUS could not be easily extended, a 64-bit side bus running at the SBUS frequency, the RBUS, was added between the SDRAM controller and those peripherals.

The static bus controller has an interface with 16-bit data and 15-bit address bus (30-bit address with an external latch) and supports SRAM, ROM, NAND Flash, NOR Flash, PCMCIA/CompactFlash devices, IDE PIO mode, and other I/O peripherals. 

The integrated LCD controller supports panels with a resolution up to 2048 × 2048 pixels.
* TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
* STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan
* Frame buffer formats:
** 1/2/4/8-bpp pass through/grayscale/palettized
** 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1, 4:4:4:0
** 24-bpp 8:8:8:0
** 32-bpp 8:8:8:8 RGBA
* Four overlay windows with double buffering
* Gamma correction, alpha blending, and chroma keying
* 32 × 32 × 2 bpp hardware cursor

The Camera Interface Module (CIM) has an [[wikipedia:ITU-R BT.656|ITU-R BT.656]] compatible 8/9/10-bit bus running at up to 33 MHz, and supports UYVY and Bayer RGB to planar format conversion.

The Media Acceleration Engine (MAE) accelerates video decoding in hardware.
* Formats MPEG-1/2/4, DivX-3/4/5, H.263, WMV9, VC-1
* Accelerates inverse quantization, inverse DCT, motion compensation, WMV9 filters
* Hardware colorspace conversion and scaling with 4-tap filter, also for CIM
* Video decode resolution up to
** Wide-CIF 480 × 288 (Au1210)
** D1 720 × 480 NTSC / 720 × 576 PAL (Au1200, Au1250)

Au12xx processors support the Hibernate mode. Au1200 and Au1250 identify with PRId 0x0403xxxx, Au1210 as 0x0503xxxx. The CPU core of Au1200 processors runs at 1.2&nbsp;V nominal (1.1-1.3&nbsp;V) and is rated for frequencies between 333 and 500&nbsp;MHz. The 400&nbsp;MHz variant has a typical TDP of 400&nbsp;mW.

The Au1210 core runs at 1.0&nbsp;V nominal (0.95-1.3&nbsp;V, compatible with the 1.2&nbsp;V Au1200 and Au1250 processors), and is rated for frequencies between 333 and 500&nbsp;MHz. The 333&nbsp;MHz variant has a typical TDP of 250 mW.

The CPU core of Au1250 processors runs at 1.2&nbsp;V nominal (1.1-1.3&nbsp;V) and is rated for frequencies between 400 and 700&nbsp;MHz.<!--Au1250-700MGD is not mentioned in the RMI Au1210/Au1250 Data Book but listed on the NetLogic and Broadcom websites.--> The 600&nbsp;MHz variant has a typical TDP of 500&nbsp;mW.

The Au12xx processors shipped in a 19&nbsp;mm × 19&nbsp;mm × 1.4&nbsp;mm, 372-pin LF-PBGA package with 0.8&nbsp;mm ball pitch. 

=== Au13xx Media Processors ===
These processors integrate the following peripherals:
* Two independent 16-bit DDR2-667 SDRAM controllers
* 16-bit static bus controller
* LCD controller
* Graphics Processing Engine (Au1350, Au1380 only)
* Enhanced Camera Interface Module
* Enhanced Media Acceleration Engine
* USB 2.0 ({{abbr|EHCI}}) and 1.1 ({{abbr|OHCI}}) host controller, USB 2.0 device controller with OTG support
** One USB host port and one host/device port, each USB 1.1/2.0 compliant
* Three [[wikipedia:SD card|Secure Digital]]/{{abbr|SDHC}}/{{abbr|SDIO}}/{{abbr|MMC}} controllers, one with 8-bit {{abbr|eMMC}} 4.3 support
* Four Programmable Serial Controllers, each supporting the {{abbr|AC97}}, {{abbr|I2S}}, {{abbr|SPI}}, and {{abbr|SMBus}} protocols
* Four {{abbr|UART}}s
* Up to 75 {{abbr|GPIO}}s
* Descriptor-based DMA controller
* AES-128 hardware encryption/decryption (Au1350, Au1380 only)

The static bus controller seems to be derived from the controller in Au12xx processors and supports ATA-6/UDMA mode 5.

The Graphics Processing Engine (GPE), an [[ARM]] [[Mali]], supposedly the [[Mali-200]], supports
* 2D graphics acceleration
* 3D graphics acceleration
** OpenGL ES 1.1 and 2.0 and OpenVG 1.1 compatible
** Vertex and Fragment shaders
** 10M polygons per second
** 4× full-screen anti-aliasing with no impact on performance
** Up to 25× FSAA supported
** Alpha blending and texture caching

The enhanced Media Acceleration Engine (MAE2) accelerates video decoding in hardware.
* Formats MPEG-1/2/4, DivX, H.264, VC-1, JPEG
* Bit Stream Accelerator to speed up bit stream parsing and entropy decoding
* Hardware colorspace conversion and scaling up to WUXGA (1920 × 1200) LCD resolution
* Video decode resolution up to
** D1 720 × 480 NTSC / 720 × 576 PAL (Au1340, Au1350)
** 720p (Au1370, Au1380)

As with Au12xx processors, the LCD, GPE, CIM, and MAE2 peripherals can access the SDRAM controllers through a pair of RBUSes. Au13xx processors again support the Hibernate mode.

The Au1340, Au1350, Au1370, and Au1380 CPU core runs at 1.0&nbsp;V nominal. The Au1340 and Au1350 core is rated for frequencies of 533 and 667&nbsp;MHz depending on model, the Au1370 and Au1380 core for 667 and 800&nbsp;MHz. These {{abbr|SoC}}s have a typical TDP of 500&nbsp;mW at 800&nbsp;MHz. The Au13xx models were available in a 537-pin LF-PBGA package, with standard or industrial temperature range as the other members of the Alchemy family, either a 17&nbsp;mm × 17&nbsp;mm package with 0.65&nbsp;mm ball pitch, or a 21&nbsp;mm × 21&nbsp;mm package with 0.8&nbsp;mm ball pitch.

[[:File:Au1300 pinmap.svg|Au13xx Pin Map]]
<!--
BOOT[0],D8,GPIO[22]/U0CTS#,C22,RNB,T1,VSS,J14
BOOT[1],A5,GPIO[23]/U0RTS#,C23,ROE#,Y3,VSS,J15
BOOT[2],A6,GPIO[24]/U0DTR#,D20,RWE#,AC1,VSS,J16
BOOT[3],B7,GPIO[25]/U2RXD,D24,SD0_CLK,E5,VSS,J17
CIM_CLK,D10,GPIO[26]/U2TXD,F21,SD0_CMD,D4,VSS,K2
CIM_D[0],A13,GPIO[27]/U3RXD,E21,SD0_DAT0,B1,VSS,K6
CIM_D[1],A12,GPIO[28]/U3TXD,B25,SD0_DAT1,C3,VSS,K9
CIM_D[2],C12,GPIO[29]/LCD_PWM0,C14,SD0_DAT2,C4,VSS,K10
CIM_D[3],D12,GPIO[30]/LCD_PWM1,D14,SD0_DAT3,E6,VSS,K11
CIM_D[4],E12,GPIO[31]/LCD_CLKIN,A22,TCK,C13,VSS,K12
CIM_D[5],A11,GPIO[32]/SD1_DAT0,K4,TC[0],A7,VSS,K13
CIM_D[6],B11,GPIO[33]/SD1_DAT1,K1,TC[1],C9,VSS,K14
CIM_D[7],C11,GPIO[34]/SD1_DAT2,J1,TC[2],A8,VSS,K15
CIM_D[8],E10,GPIO[35]/SD1_DAT3,J2,TC[3],E9,VSS,K16
CIM_D[9],A10,GPIO[36]/SD1_CMD,J3,TDI,E14,VSS,K17
D0_A[0],AB8,GPIO[37]/SD1_CLK,K3,TDO,A14,VSS,K20
D0_A[1],AE5,GPIO[38]/SD2_DAT0,F4,TESTEN[0],B9,VSS,K24
D0_A[2],AE6,GPIO[39]/SD2_DAT1,D2,TESTEN[1],E13,VSS,L9
D0_A[3],AB6,GPIO[40]/SD2_DAT2,C1,TMS,B13,VSS,L10
D0_A[4],AA6,GPIO[41]/SD2_DAT3,E4,TRST#,A15,VSS,L11
D0_A[5],AC6,GPIO[42]/SD2_CMD,C2,U0RXD,E20,VSS,L12
D0_A[6],AA7,GPIO[43]/SD2_CLK,E3,U0TXD,D25,VSS,L13
D0_A[7],AC7,GPIO[44]/PSC0_CLK,M25,USBATEST,N23,VSS,L14
D0_A[8],AE7,GPIO[45]/PSC1_CLK,K25,USBDM,T25,VSS,L15
D0_A[9],AE8,GPIO[46]/PSC0_SYNC0,L21,USBDP,T24,VSS,L16
D0_A[10],AA8,GPIO[47]/PSC0_SYNC1,L23,USBHM,N24,VSS,L17
D0_A[11],AA9,GPIO[48]/PSC0_D0,L24,USBHP,N25,VSS,M2
D0_A[12],AD9,GPIO[49]/PSC0_D1,L25,USBOTGID,U24,VSS,M6
D0_A[13],AE9,GPIO[50]/PSC1_SYNC0,K22,USBVBUS,U25,VSS,M9
D0_BA[0],AC9,GPIO[51]/PSC1_SYNC1,K23,USBVDDI,R20,VSS,M10
D0_BA[1],AC8,GPIO[52]/PSC1_D0,J25,USBVDDI,T21,VSS,M11
D0_BA[2],AD7,GPIO[53]/PSC1_D1,K21,USBVDDX,P22,VSS,M12
D0_CAS#,AB10,GPIO[54]/PSC2_SYNC0,H25,USBVDDX,P23,VSS,M13
D0_CK,AD17,GPIO[55]/PSC2_SYNC1,J23,USBVDDX,R21,VSS,M14
D0_CK#,AE17,GPIO[56]/PSC2_D0,J21,USBVDDX,R22,VSS,M15
D0_CKE,AE10,GPIO[57]/PSC2_D1,H23,USBVDDX,T22,VSS,M16
D0_CS#,AC10,GPIO[58]/PSC3_SYNC0,H21,USBVDDX,T23,VSS,M17
D0_DM[0],AC16,GPIO[58]/U1RTS#,F23,USBVDDX,U22,VSS,M20
D0_DM[1],AC13,GPIO[59]/PSC3_SYNC1,H22,USBVDDX,V21,VSS,M24
D0_DQS[0],AE15,GPIO[60]/PSC3_D0,G23,USBXI,R25,VSS,N9
D0_DQS[0]#,AE14,GPIO[61]/PSC3_D1,G24,USBXO,R24,VSS,N10
D0_DQS[1],AA13,GPIO[62]/PCE[2]#,L2,USB_RKELVIN,P25,VSS,N11
D0_DQS[1]#,AA14,GPIO[63]/PCE[1]#,L3,VDDI,F7,VSS,N12
D0_DQ[0],AC15,GPIO[64]/PIOS16#,M5,VDDI,F9,VSS,N13
D0_DQ[1],AC12,GPIO[65]/PIOR#,M4,VDDI,F11,VSS,N14
D0_DQ[2],AD15,GPIO[66]/PWE#,N2,VDDI,F13,VSS,N15
D0_DQ[3],AB14,GPIO[67]/PWAIT#,N5,VDDI,F15,VSS,N16
D0_DQ[4],AD13,GPIO[68]/PREG#,M1,VDDI,F17,VSS,N17
D0_DQ[5],AE13,GPIO[69]/POE#,M3,VDDI,F19,VSS,P2
D0_DQ[6],AE12,GPIO[70]/PIOW#,N1,VDDI,G6,VSS,P6
D0_DQ[7],AD11,GPIO[71]/CIM_LS,E11,VDDI,G20,VSS,P9
D0_DQ[8],AB16,GPIO[72]/CIM_FS,C10,VDDI,J6,VSS,P10
D0_DQ[9],AA15,GPIO[73]/PSC2_CLK,J24,VDDI,J20,VSS,P11
D0_DQ[10],AA16,GPIO[74]/PSC3_CLK,G25,VDDI,L6,VSS,P12
D0_DQ[11],AE11,HD_CS[0]#,L5,VDDI,L20,VSS,P13
D0_DQ[12],AC11,HD_CS[1]#,L1,VDDI,N6,VSS,P14
D0_DQ[13],AB12,LCD_BIAS,B19,VDDI,N20,VSS,P15
D0_DQ[14],AE16,LCD_D[0],E15,VDDI,R6,VSS,P16
D0_DQ[15],AA12,LCD_D[1],B15,VDDI,U6,VSS,P17
D0_RAS#,AA10,LCD_D[2],A16,VDDI,U20,VSS,P20
D0_WE#,AA11,LCD_D[3],A17,VDDI,W6,VSS,P24
D1_A[0],AA25,LCD_D[4],C15,VDDI,W20,VSS,R9
D1_A[1],W25,LCD_D[5],E16,VDDI,Y7,VSS,R10
D1_A[2],W24,LCD_D[6],A18,VDDI,Y9,VSS,R11
D1_A[3],V25,LCD_D[7],B17,VDDI,Y11,VSS,R12
D1_A[4],U21,LCD_D[8],C16,VDDI,Y13,VSS,R13
D1_A[5],V24,LCD_D[9],D16,VDDI,Y15,VSS,R14
D1_A[6],V23,LCD_D[10],E17,VDDI,Y17,VSS,R15
D1_A[7],V22,LCD_D[11],A19,VDDI,Y19,VSS,R16
D1_A[8],Y23,LCD_D[12],B21,VDDX,D3,VSS,R17
D1_A[9],AB25,LCD_D[13],A23,VDDX,D5,VSS,R23
D1_A[10],W23,LCD_D[14],C18,VDDX,D7,VSS,T2
D1_A[11],W21,LCD_D[15],E18,VDDX,D9,VSS,T6
D1_A[12],AA23,LCD_D[16],D18,VDDX,D11,VSS,T9
D1_A[13],AC25,LCD_D[17],A24,VDDX,D13,VSS,T10
D1_BA[0],Y22,LCD_D[18],A25,VDDX,D15,VSS,T11
D1_BA[1],AA24,LCD_D[19],C19,VDDX,D17,VSS,T12
D1_BA[2],Y25,LCD_D[20],E19,VDDX,D19,VSS,T13
D1_CAS#,AC24,LCD_D[21],C21,VDDX,D21,VSS,T14
D1_CK,AB22,LCD_D[22],C20,VDDX,D23,VSS,T15
D1_CK#,AC23,LCD_D[23],B23,VDDX,G4,VSS,T16
D1_CKE,AB23,LCD_FCLK,C17,VDDX,G22,VSS,T17
D1_CS#,AD25,LCD_LCLK,A20,VDDX,J4,VSS,T20
D1_DM[0],AC19,LCD_PCLK,A21,VDDX,J22,VSS,U9
D1_DM[1],AB18,NC,A1,VDDX,L4,VSS,U10
D1_DQS[0],AE21,OTP_CS#/FTM_SEL#,P21,VDDX,L22,VSS,U11
D1_DQS[0]#,AE22,OTP_PGM/FTM_DAT,M23,VDDX,N4,VSS,U12
D1_DQS[1],AD21,OTP_SCLK/FTM_CLK,M21,VDDX,N22,VSS,U13
D1_DQS[1]#,AC20,OTP_VDDQ25/FTM_PWR,N21,VDDX,R4,VSS,U14
D1_DQ[0],AE18,OTP_WPROT/FTM_EN#,M22,VDDX,U4,VSS,U15
D1_DQ[1],AE19,PWR_EN,F5,VDDX,W4,VSS,U16
D1_DQ[2],AD19,RAD[0],W2,VDDXOK,AE4,VSS,U17
D1_DQ[3],AB20,RAD[1],T4,VDDY,W22,VSS,U23
D1_DQ[4],AC21,RAD[2],U5,VDDY,AA22,VSS,V2
D1_DQ[5],AE24,RAD[3],Y1,VDDY,AB5,VSS,V6
D1_DQ[6],AD23,RAD[4],W1,VDDY,AB7,VSS,V20
D1_DQ[7],AC18,RAD[5],T3,VDDY,AB9,VSS,Y2
D1_DQ[8],AC17,RAD[6],U2,VDDY,AB11,VSS,Y6
D1_DQ[9],AA17,RAD[7],U3,VDDY,AB13,VSS,Y8
D1_DQ[10],AC22,RAD[8],T5,VDDY,AB15,VSS,Y10
D1_DQ[11],AE25,RAD[9],V1,VDDY,AB17,VSS,Y12
D1_DQ[12],AA18,RAD[10],R2,VDDY,AB19,VSS,Y14
D1_DQ[13],AE23,RAD[11],P4,VDDY,AB21,VSS,Y16
D1_DQ[14],AA19,RAD[12],R5,VDDY,AD24,VSS,Y18
D1_DQ[15],AE20,RAD[13],R3,VSS,B2,VSS,Y20
D1_RAS#,Y21,RAD[14],U1,VSS,B4,VSS,Y24
D1_WE#,AA21,RALE,AB1,VSS,B6,VSS,AB2
DDRIVE_PADHI,AD5,RBE[0]#,V3,VSS,B8,VSS,AB24
DDRIVE_PADLO,AC5,RBE[1]#,AA1,VSS,B10,VSS,AD2
D_VREF,AA20,RCLE,AA2,VSS,B12,VSS,AD4
D_VREF,AC14,RCLK,V4,VSS,B14,VSS,AD6
EWAIT#,P3,RCS[0]#,R1,VSS,B16,VSS,AD8
FTM,A9,RCS[1]#,N3,VSS,B18,VSS,AD10
FWTOY#,J5,RCS[2]#,P5,VSS,B20,VSS,AD12
GPIO[0]/SLEEPWAKE[0],E7,RCS[3]#,P1,VSS,B22,VSS,AD14
GPIO[1]/SLEEPWAKE[1],C6,RDMACK#,V5,VSS,B24,VSS,AD16
GPIO[2]/SLEEPWAKE[2],E8,RDMARQ,W3,VSS,F2,VSS,AD18
GPIO[3]/SLEEPWAKE[3],B5,RD[0],AA5,VSS,F6,VSS,AD20
GPIO[4]/EXTCLK0,A4,RD[1],AB4,VSS,F8,VSS,AD22
GPIO[5]/EXTCLK1,C7,RD[2],Y5,VSS,F10,WAKE#,K5
GPIO[6]/SD0_DAT4,D6,RD[3],AA4,VSS,F12,XAGND12,F3
GPIO[7]/SD0_DAT5,A2,RD[4],AE2,VSS,F14,XAGND32,F1
GPIO[8]/SD0_DAT6,C5,RD[5],Y4,VSS,F16,XAGNDAUXPLL,G3
GPIO[9]/SD0_DAT7,A3,RD[6],W5,VSS,F18,XAGNDCPUPLL,H5
GPIO[10],B3,RD[7],AC2,VSS,F20,XPWR12,D1
GPIO[11]/U1RI#,G21,RD[8],AC4,VSS,F24,XPWR32,H1
GPIO[12]/U1DCD#,F25,RD[9],AE3,VSS,H2,XPWRAUXPLL,G5
GPIO[13]/U1DSR#,C25,RD[10],AD3,VSS,H6,XPWRCPUPLL,H4
GPIO[14]/U1CTS#,D22,RD[11],AC3,VSS,H20,XTI12,E1
GPIO[16]/U1DTR#,E25,RD[12],AB3,VSS,H24,XTI32,G2
GPIO[17]/U1RXD,C24,RD[13],AE1,VSS,J9,XTO12,E2
GPIO[18]/U1TXD,E24,RD[14],AA3,VSS,J10,XTO32,G1
GPIO[19]/U0RI#,E22,RD[15],AD1,VSS,J11
GPIO[20]/U0DCD#,E23,RESETIN#,H3,VSS,J12
GPIO[21]/U0DSR#,F22,RESETOUT#,C8,VSS,J13
-->

== List of Alchemy Processors ==
<!-- NOTE:
  This table is generated automatically from the data in the actual articles.
  If a microprocessor is missing from the list, an appropriate article for it needs to be
  created and tagged accordingly.
  Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable">
{{comp table header|cols|Process|Core Frequ.|V<sub>core</sub>|SDRAM|T<sub>case min</sub>|T<sub>case max</sub>|{{abbr|TDP}} typ.|TDP max.|Rel. price (10k)}}
{{#ask: [[instance of::microprocessor]] [[microarchitecture::Au1]]
 |?full page name
 |?model number
 |?process
 |?base frequency#MHz
 |?core voltage#V
 |?supported memory type
 |?min case temperature#°C |?max case temperature#°C
 |?tdp (typical)#mW |?tdp#mW
 |?release price (tray)
 |sort=model number
 |format=template
 |template=proc table 3
 |userparam=11
 |mainlabel=-
}}
{{comp table count|ask=[[instance of::microprocessor]] [[microarchitecture::Au1]]}}
</table>
{{comp table end}}

=== List of Au13xx processors ===
<!-- If you have a copy of the Au13xx Data Book please upload. The data here is from the NetLogic & Broadcom website, a few additional part numbers (not descriptions, they're mismatched) from Mouser. -->
{| class="wikitable sortable"
! Model
! Part Number
! Core Frequ.
! {{abbr|GPE|Graphics Processing Engine}}
! Temp. Range
! {{abbr|TDP}}
! Package<ref>LBA537 17×17&nbsp;mm, 0.65&nbsp;mm pitch; LBA537 21×21&nbsp;mm, 0.8&nbsp;mm pitch</ref>
! {{abbr|LTB|Last Time Buy}}
|-
| Au1310-533MBD || AU1310-533MBDA2 || 533 MHz || || || || ||
|-
| Au1310-533MTD || AU1310-533MTDA2 || 533 MHz || || Commercial || || ||
|-
| Au1310-667MBD || AU1310-667MBDA2 || 667 MHz || {{tchk|no}} || Commercial || || 21×21&nbsp;mm ||
|-
| Au1320-667MTJ || AU1320-667MTJA2 || 667 MHz || {{tchk|yes}} || Industrial || || 21×21&nbsp;mm Therm Enh ||
|-
| Au1340-533MBD || AU1340-533MBDA2 || 533 MHz || {{tchk|no}} || || || ||
|-
| Au1340-667MBD || AU1340-667MBDA2 || 667 MHz || {{tchk|no}} || Commercial || || 21×21&nbsp;mm ||
|-
| Au1340-667MBJ || || 667 MHz || {{tchk|no}} || || || ||
|-
| Au1340-667MTD || AU1340-667MTDA2 || 667 MHz || {{tchk|no}} || Commercial || || ||
|-
| Au1340-667MTJ || AU1340-667MTJA2 || 667 MHz || {{tchk|no}} || Industrial || ||
| 2017-12<ref name="eol17">Broadcom Product Obsolescence Notification EOL-CCX-42972-146-0, August 25, 2017</ref>
|-
| Au1350-533MBD || AU1350-533MBDA2 || 533 MHz || {{tchk|yes}} || || || ||
|-
| Au1350-667MBD || AU1350-667MBDA2 || 667 MHz || {{tchk|yes}} || || || ||
|-
| Au1350-667MBJ || AU1350-667MBJA2 || 667 MHz || {{tchk|yes}} || Industrial || || 21×21&nbsp;mm || 2017-12<ref name="eol17"/>
|-
| Au1350-667MTD || AU1350-667MTDA2 || 667 MHz || {{tchk|yes}} || Commercial || || 21×21&nbsp;mm Therm Enh ||
|-
| Au1354-800MTD || AU1354-800MTDA2 || 800 MHz || || Commercial || || ||
|-
| Au1354-800MTX || AU1354-800MTXA2 || 800 MHz || || Extended || || ||
|-
| Au1370-667MBJ || AU1370-667MBJA2 || 667 MHz || {{tchk|no}} || Industrial || || 21×21&nbsp;mm ||
|-
| Au1370-667MHD || AU1370-667MHDA2 || 667 MHz || {{tchk|no}} || Commercial || || 17×17&nbsp;mm ||
|-
| Au1370-800MBD || AU1370-800MBDA2 || 800 MHz || {{tchk|no}} || || || ||
|-
| Au1370-800MTD || AU1370-800MTDA2 || 800 MHz || {{tchk|no}} || Commercial || || ||
|-
| Au1370-1000MFD || AU1370-1000MFDA2 || || {{tchk|no}} || || || ||
|-
| Au1374-800MBD || AU1374-800MBDA2 || 800 MHz || || || || ||
|-
| Au1374-800MTD || AU1374-800MTDA2 || 800 MHz || || Commercial || || ||
|-
| Au1380-667MBD || AU1380-667MBDA2 || 667 MHz || {{tchk|yes}} || || || 21×21&nbsp;mm ||
|-
| Au1380-667MTD || AU1380-667MTDA2 || 667 MHz || {{tchk|yes}} || Commercial || || 21×21&nbsp;mm Therm Enh ||
|-
| Au1380-800MBD || AU1380-800MBDA2 || 800 MHz || {{tchk|yes}} || Commercial || || 21×21&nbsp;mm ||
|-
| Au1380-800MFD || AU1380-800MFDA2 || 800 MHz || {{tchk|yes}} || Commercial || || ||
|-
| Au1380-1000MFD || AU1380-1000MFDA2 || 1000 MHz || {{tchk|yes}} || Commercial || || ||
|-
| Au1384-800MBD || AU1384-800MBDA2 || 800 MHz || || || || ||
|-
| Au1384-800MBJ || AU1384-800MBJA2 || 800 MHz || || || || ||
|-
| Au1384-800MFJ || AU1384-800MFJA2 || 800 MHz || || Industrial || || || 2017-12<ref name="eol17"/>
|-
| Au1384-800MTD || AU1384-800MTDA2 || 800 MHz || || Commercial || || ||
|-
| Au1384-800MTX || AU1384-800MTXA2 || || || || || 21×21&nbsp;mm PBGA+HS ||
|}
<references/>

== Bibliography ==
* {{cite techdoc|title=AMD Alchemy™ Au1000™ Processor Data Book|url=https://web.archive.org/web/20061015230659id_/http://www.razamicroelectronics.com/pub_assets/30360D_au1000_databook.pdf|publ=AMD|pid=30360|rev=D|date=2005-09}}
* {{cite techdoc|title=AMD Alchemy™ Au1100™ Processor Data Book|url=https://web.archive.org/web/20061020095828id_/http://www.amd.com:80/files/connectivitysolutions/aufamily/au1100/30362D_au1100_databook.pdf|publ=AMD|pid=30362|rev=D|date=2006-04}}
* {{cite techdoc|title=AMD Alchemy™ Au1200™ Processor Data Book|url=https://web.archive.org/web/20061015230051id_/http://www.razamicroelectronics.com/pub_assets/32798e_Au1200_ds.pdf|publ=AMD|pid=32798|rev=E|date=2006-02}}
* {{cite techdoc|authors=Eno, Jim|title=White Paper: AMD Alchemy™ Au1200™ Processor System Architecture|url=https://web.archive.org/web/20051223152802id_/http://www.amd.com:80/files/connectivitysolutions/aufamily/au1200/32785a_au1200sysarch_wpaper.pdf|publ=AMD|pid=32785|rev=A|date=2005}}
* {{cite techdoc|title=RMI Alchemy™ Au1210™ Navigation Processor and Au1250™ Media Processor Data Book|file=RMI-Au1210-Au1250-DB.pdf|publ=RMI Corp.|rev=A|date=2007-04}}
* {{cite techdoc|title=Product Brief: RMI Alchemy™ Au1300™ Media Processor Series|file=RMI-Au1300-PB.pdf|publ=RMI Corp.|rev=A|date=2008-12}}
* [https://web.archive.org/web/20101213050823/http://www.netlogicmicro.com/Products/ProductBriefs/Alchemy/ULPP%20Guide.htm "NetLogic Microsystems Low-Power Embedded Processors Solution and Product Selection Guide"], netlogicmicro.com, archived December 13, 2010
* {{cite techdoc|title=AMD Alchemy™ Au1500™ Processor Data Book|url=https://web.archive.org/web/20061015230435id_/http://www.razamicroelectronics.com/pub_assets/30361D_au1500_db.pdf|publ=AMD|pid=30361|rev=D|date=2006-03}}
* {{cite techdoc|title=AMD Alchemy™ Au1550™ Security Network Processor Data Book|url=https://web.archive.org/web/20060708150440id_/http://www.amd.com:80/files/connectivitysolutions/aufamily/au1550/30283D_Au1550_db.pdf|publ=AMD|pid=30283|rev=D|date=2006-05}}

Alchemy Semiconductor publications:
* {{cite techdoc|authors=Hoeppner, Greg|title=Au1000 Internet Edge Processor|file=Au1000 Internet Edge Processor presentation.ppt|publ=Embedded Processor Forum 2000|date=2000-06-13}}
* {{cite techdoc|authors=Plummer, Suzanne|title=The Au1000™ Internet Edge Processor: A High Performance, Low Power SOC|url=https://hc12.hotchips.org|publ=Hot Chips 12|date=2000-08-13}}
* {{cite techdoc|title=Product Brief: The Alchemy Au1000™ Internet Edge Processor|file=Alchemy-Au1000-PB.pdf|publ=Alchemy|date=2000}}
* {{cite techdoc|title=Product Brief: The Alchemy Au1500™ Internet Edge Processor|file=Alchemy-Au1500-PB.pdf|publ=Alchemy|date=2001}}
* [https://web.archive.org/web/20000816094552/http://www.alchemysemi.com:80/ http://www.alchemysemi.com] (archived)

AMD publications:
* See [[amd/List of AMD publications|List of AMD publications]]
* [http://web.archive.org/web/20060203023239/http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_6625,00.html "AMD Alchemy™ Solutions Processor Family"], AMD.com, archived February 3, 2006

RMI publications:
* [https://web.archive.org/web/20040210003336/http://www.razamicroelectronics.com:80/ http://www.razamicroelectronics.com] (archived)
* [https://web.archive.org/web/20080210001717/http://www.rmicorp.com:80/ http://www.rmicorp.com] (archived)

NetLogic publications:
* [https://web.archive.org/web/20101214233835/http://www.netlogicmicro.com:80/Products/Alchemy/index.asp "Ultra Low-Power Embedded Processor Family"], netlogicmicro.com, archived December 14, 2010

== See also ==
* [[DEC]] {{decc|StrongARM}}
* [[Intel]] {{intel|XScale}}
designer	Alchemy +, AMD + and RMI +
first announced	June 13, 2000 +
full page name	alchemy/alchemy +
instance of	integrated circuit family +
main designer	Alchemy +
manufacturer	TSMC +
microarchitecture	Au1 +
name	Alchemy +
process	180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +