Editing Talk:nec/microarchitectures/sx-aurora

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== 256 physical vector registers? ==

Where does this information come from?

I've not seen such a claim anywhere else, and frankly it does not make a lot of sense to me. That would make the vector register a whopping 256×256×8bytes = 8MBytes.

More importantly, it would take 192 register renames to use each register at least once. It would need an extraordinarily large reorder buffer to make this happen.

And as there are still unused bits in the instruction format, much better use could be made of those registers by at least partially exposing that large register file to the user. In fact, what made me comment here is that I'd be angry at NEC's hardware engineers to not at least expose 128 architectural hardware registers if 256 physical registers existed.

Taking all that together, I suspect the 256 physical vector registers per Vector Processing Unit don't in fact exist. [[Special:Contributions/2.26.148.69|2.26.148.69]] 15:45, 22 April 2020 (EDT)

== Cache bandwidth listed as 3GB/s ==

i believe there is a typo stating the LLC bandwidth as 3GB/s when it should be 3TB/s

:That's correct. Thank you. --[[User:David|David]] ([[User talk:David|talk]]) 23:08, 13 May 2020 (EDT)