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| {{lithography processes}} | | {{lithography processes}} |
− | The '''8 µm lithography process''' (8-micron) was the semiconductor process technology used for early FET devices by leading semiconductor companies during the late early 1970s. This process had a smallest feature or gate length of roughly 8 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm). This process was later superseded by [[6 µm]], [[5 µm]], and [[3 µm]] processes. | + | The '''8 µm lithography process''' was the semiconductor process technology used by some semiconductor companies during the late 1960s through the early 1970s. The typical [[wafer]] size for this process at companies such as [[Fairchild]] and [[TI]] were 2 inch (51 mm). This process was later superseded by [[6 µm]], [[5 µm]], and [[3 µm]] processes. |
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| == Industry == | | == Industry == |
− | The 8-micron process was used by Intel for many of their memory chips in the early 1970s such as the {{intel|2104}} which was released in 1972 and became the first truly widely used DRAM chip. Those chips used Si-gate [[nMOS]] transistors using a polysilicon word line and an aluminum metal bit line. Alternatively to that was Mostek's which created a 4 Kib chip using an aluminum metal word line and drain diffusion for the bit line<ref>Rideout, V. Leo. "One-device cells for dynamic random-access memories: A tutorial." IEEE Transactions on Electron Devices 26.6 (1979): 839-852.</ref>.
| + | {{scrolling table/top|style=text-align: right; | first=Fab |
− | | + | |Process Name |
− | {{#invoke:process nodes
| + | |1st Production |
− | | compare
| + | |Contacted Gate Pitch |
− | | fab 1 name link = intel
| + | |Interconnect Pitch |
− | | fab 1 proc name =
| + | |Metal Layers |
− | | fab 1 name = Intel
| + | |Technology |
− | | fab 1 date = 1972
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− | | fab 1 wafer.type = Bulk
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− | | fab 1 wafer.size = 51 mm
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− | | fab 1 xtor.tech = nMOS, pMOS
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− | | fab 1 xtor.type = Planar
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− | | fab 1 xtor.volt = 5 V
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− | | fab 1 layers = 1, 2
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− | | fab 1 diff from = [[10 µm]] Δ
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− | | fab 1 xtor.lg = 8 µm
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− | | fab 1 xtor.lgΔ = 0.80x | |
− | | fab 1 xtor.cpp = | |
− | | fab 1 xtor.cppΔ = | |
− | | fab 1 xtor.mmp = | |
− | | fab 1 xtor.mmpΔ = | |
− | | fab 1 sram.hp = | |
− | | fab 1 sram.hpΔ =
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− | | fab 1 sram.hd = 1280 µm²
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− | | fab 1 sram.hdΔ =
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− | | fab 1 sram.lv =
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− | | fab 1 sram.lvΔ =
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− | | fab 1 dram.edram =
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− | | fab 1 dram.edramΔ =
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− | | |
− | | fab 2 name link = ti
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− | | fab 2 name = TI
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− | | fab 2 proc name =
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− | | fab 2 date =
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− | | fab 2 wafer.type = Bulk
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− | | fab 2 wafer.size =
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− | | fab 2 xtor.tech = pMOS
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− | | fab 2 xtor.type = Planar
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− | | fab 2 xtor.volt = 5 V
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− | | fab 2 layers =
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− | | fab 2 diff from = [[10 µm]] Δ
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− | | fab 2 xtor.lg = 8 µm
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− | | fab 2 xtor.lgΔ = 0.80x
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− | | fab 2 xtor.cpp =
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− | | fab 2 xtor.cppΔ =
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− | | fab 2 xtor.mmp =
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− | | fab 2 xtor.mmpΔ =
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− | | fab 2 sram.hp =
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− | | fab 2 sram.hpΔ =
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− | | fab 2 sram.hd =
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− | | fab 2 sram.hdΔ =
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− | | fab 2 sram.lv =
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− | | fab 2 sram.lvΔ =
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− | | fab 2 dram.edram =
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− | | fab 2 dram.edramΔ =
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− | | |
− | | fab 3 name link = fairchild
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− | | fab 3 name = Fairchild
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− | | fab 3 proc name =
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− | | fab 3 date =
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− | | fab 3 wafer.type = Bulk
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− | | fab 3 wafer.size =
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− | | fab 3 xtor.tech = pMOS
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− | | fab 3 xtor.type = Planar
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− | | fab 3 xtor.volt = 5 V
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− | | fab 3 layers =
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− | | fab 3 diff from = [[10 µm]] Δ
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− | | fab 3 xtor.lg = 8 µm
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− | | fab 3 xtor.lgΔ = 0.80x
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− | | fab 3 xtor.cpp =
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− | | fab 3 xtor.cppΔ =
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− | | fab 3 xtor.mmp =
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− | | fab 3 xtor.mmpΔ =
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− | | fab 3 sram.hp =
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− | | fab 3 sram.hpΔ =
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− | | fab 3 sram.hd =
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− | | fab 3 sram.hdΔ =
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− | | fab 3 sram.lv =
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− | | fab 3 sram.lvΔ =
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− | | fab 3 dram.edram =
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− | | fab 3 dram.edramΔ =
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− | | |
− | | fab 4 name link = mos technology
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− | | fab 4 name = MOS Technology
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− | | fab 4 proc name =
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− | | fab 4 date = 1974
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− | | fab 4 wafer.type = Bulk
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− | | fab 4 wafer.size =
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− | | fab 4 xtor.tech = nMOS
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− | | fab 4 xtor.type = Planar
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− | | fab 4 xtor.volt = 5 V
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− | | fab 4 layers =
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− | | fab 4 diff from = @
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− | | fab 4 xtor.lg = 8 µm
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− | | fab 4 xtor.lgΔ =
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− | | fab 4 xtor.cpp =
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− | | fab 4 xtor.cppΔ =
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− | | fab 4 xtor.mmp =
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− | | fab 4 xtor.mmpΔ =
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− | | fab 4 sram.hp =
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− | | fab 4 sram.hpΔ =
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− | | fab 4 sram.hd =
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− | | fab 4 sram.hdΔ =
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− | | fab 4 sram.lv =
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− | | fab 4 sram.lvΔ =
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− | | fab 4 dram.edram =
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− | | fab 4 dram.edramΔ =
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− | | |
− | | fab 5 name link = mostok
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− | | fab 5 name = MOSTEK
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− | | fab 5 proc name =
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− | | fab 5 date = 1972
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− | | fab 5 wafer.type = Bulk
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− | | fab 5 wafer.size =
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− | | fab 5 xtor.tech = nMOS
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− | | fab 5 xtor.type = Planar
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− | | fab 5 xtor.volt = 5 V
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− | | fab 5 layers =
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− | | fab 5 diff from = @
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− | | fab 5 xtor.lg = 8 µm
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− | | fab 5 xtor.lgΔ =
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− | | fab 5 xtor.cpp =
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− | | fab 5 xtor.cppΔ =
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− | | fab 5 xtor.mmp =
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− | | fab 5 xtor.mmpΔ =
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− | | fab 5 sram.hp =
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− | | fab 5 sram.hpΔ =
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− | | fab 5 sram.hd =
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− | | fab 5 sram.hdΔ =
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− | | fab 5 sram.lv =
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− | | fab 5 sram.lvΔ =
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− | | fab 5 dram.edram =
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− | | fab 5 dram.edramΔ =
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| }} | | }} |
| + | {{scrolling table/mid}} |
| + | |- |
| + | ! [[Intel]] !! [[TI]] !! [[Fairchild]] !! [[MOS Technology]] |
| + | |- style="text-align: center;" |
| + | | || || || |
| + | |- style="text-align: center;" |
| + | | 1970 || 1969 || 1969 || 1974 |
| + | |- |
| + | | ? nm || ? nm || ? nm || ? nm |
| + | |- |
| + | | ? nm || ? nm || ? nm || ? nm |
| + | |- |
| + | | 2 || 2 || 2 || |
| + | |- |
| + | | pMOS || pMOS || pMOS || depletion-mode nMOS |
| + | {{scrolling table/end}} |
| | | |
− | == 8 µm Microprocessors == | + | == Microprocessors == |
| * TI | | * TI |
| ** {{ti|TMS1000}} | | ** {{ti|TMS1000}} |
| * MOS Technology | | * MOS Technology |
| ** {{mos tech|MCS6500}} | | ** {{mos tech|MCS6500}} |
− | {{expand list}}
| |
| | | |
| == 8 µm Chips == | | == 8 µm Chips == |
| * Intel | | * Intel |
− | ** {{intel|1103}}, 1 Kib DRAM, world's first commercial DRAM | + | ** {{intel|1103}}, 1Kb DRAM, worlds first commercial DRAM |
− | ** {{intel|2104}}, 4 Kib DRAM, world first widely used & mass produced (especially in the [[personal computer|PC]])
| + | |
| | | |
− | == References ==
| |
− | {{reflist}}
| |
− | * Dr. Neil Berglund, Intel Corporation; The evolution of MOS process technology.
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| {{stub}} | | {{stub}} |
− | [[category:lithography]] | + | [[Category:Lithography]] |