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| | {{lithography processes}} | | {{lithography processes}} |
| − | The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023. | + | The '''3.5 nanometer (3.5 nm)''' or '''35 Å lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[technology node|gate length or half pitch]]. |
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| − | The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | |
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| | == Industry == | | == Industry == |
| | + | {{empty section}} |
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| − | {{future information}}
| + | == 3.5 nm Microprocessors== |
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| − | {{finfet nodes comp
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| − | <!-- Intel -->
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| − | | process 1 fab = [[Intel]]
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| − | | process 1 name = P1278 (CPU), P1279? (SoC)
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| − | | process 1 date = 2H 2023
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| − | | process 1 lith = EUV
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| − | | process 1 immersion =
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| − | | process 1 exposure = SE
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| − | | process 1 wafer type = Bulk
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| − | | process 1 wafer size = 300 mm
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| − | | process 1 transistor = FinFET
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| − | | process 1 volt =
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| − | | process 1 delta from = [[5 nm]] Δ
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| − | | process 1 fin pitch =
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| − | | process 1 fin pitch Δ =
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| − | | process 1 fin width =
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| − | | process 1 fin width Δ =
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| − | | process 1 fin height =
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| − | | process 1 fin height Δ =
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| − | | process 1 gate len =
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| − | | process 1 gate len Δ =
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| − | | process 1 cpp =
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| − | | process 1 cpp Δ =
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| − | | process 1 mmp =
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| − | | process 1 mmp Δ =
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| − | | process 1 sram hp =
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| − | | process 1 sram hp Δ =
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| − | | process 1 sram hd =
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| − | | process 1 sram hd Δ =
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| − | | process 1 sram lv =
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| − | | process 1 sram lv Δ =
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| − | | process 1 dram =
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| − | | process 1 dram Δ =
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| − | <!-- TSMC -->
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| − | | process 2 fab = [[TSMC]]
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| − | | process 2 name = N3, N3E <info>N3 Enhanced</info>
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| − | | process 2 date = 2H 2022
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| − | | process 2 lith = EUV
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| − | | process 2 immersion =
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| − | | process 2 exposure = SE
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| − | | process 2 wafer type = Bulk
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| − | | process 2 wafer size = 300 mm
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| − | | process 2 transistor = FinFET
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| − | | process 2 volt =
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| − | | process 2 delta from = [[5 nm]] Δ
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| − | | process 2 fin pitch =
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| − | | process 2 fin pitch Δ =
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| − | | process 2 fin width =
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| − | | process 2 fin width Δ =
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| − | | process 2 fin height =
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| − | | process 2 fin height Δ =
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| − | | process 2 gate len =
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| − | | process 2 gate len Δ =
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| − | | process 2 cpp =
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| − | | process 2 cpp Δ =
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| − | | process 2 mmp =
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| − | | process 2 mmp Δ =
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| − | | process 2 sram hp =
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| − | | process 2 sram hp Δ =
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| − | | process 2 sram hd =
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| − | | process 2 sram hd Δ =
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| − | | process 2 sram lv =
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| − | | process 2 sram lv Δ =
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| − | | process 2 dram =
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| − | | process 2 dram Δ =
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| − | <!-- Samsung -->
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| − | | process 4 fab = [[Samsung]]
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| − | | process 4 name = 3GAE<info>3nm Gate All Around Early</info>, 3GAP<info>3nm Gate All Around Plus</info>
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| − | | process 4 date =
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| − | | process 4 lith = EUV
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| − | | process 4 immersion =
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| − | | process 4 exposure = SE
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| − | | process 4 wafer type = Bulk
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| − | | process 4 wafer size = 300 mm
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| − | | process 4 transistor = GAA
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| − | | process 4 volt =
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| − | | process 4 delta from = [[5 nm]] Δ
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| − | | process 4 fin pitch = -
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| − | | process 4 fin pitch Δ =
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| − | | process 4 fin width =
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| − | | process 4 fin width Δ =
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| − | | process 4 fin height =
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| − | | process 4 fin height Δ =
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| − | | process 4 gate len =
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| − | | process 4 gate len Δ =
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| − | | process 4 cpp =
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| − | | process 4 cpp Δ =
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| − | | process 4 mmp =
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| − | | process 4 mmp Δ =
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| − | | process 4 sram hp =
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| − | | process 4 sram hp Δ =
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| − | | process 4 sram hd =
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| − | | process 4 sram hd Δ =
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| − | | process 4 sram lv =
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| − | | process 4 sram lv Δ =
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| − | | process 4 dram =
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| − | | process 4 dram Δ =
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| − | }}
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| − | ==== P1278 ====
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| − | Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe.
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| − | === Samsung ===
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| − | On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
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| − | === TSMC ===
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| − | N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2.
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| − | == 3 nm Microprocessors==
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| | {{expand list}} | | {{expand list}} |
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| − | == 3 nm Microarchitectures== | + | == 3.5 nm Microarchitectures== |
| | {{expand list}} | | {{expand list}} |
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| − | == References ==
| + | [[Category:Lithography]] |
| − | * Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after [[5 nm]], May 24, 2017
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| − | | |
| − | [[category:lithography]]
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