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Latest revision | Your text | ||
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| process 1 lith = 193 nm | | process 1 lith = 193 nm | ||
| process 1 immersion = Yes | | process 1 immersion = Yes | ||
− | | process 1 exposure = | + | | process 1 exposure = SADP |
| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
| process 1 transistor = Planar | | process 1 transistor = Planar | ||
− | | process 1 volt = | + | | process 1 volt = |
− | |||
| process 1 delta from = [[45 nm]] Δ | | process 1 delta from = [[45 nm]] Δ | ||
− | | process 1 gate len = | + | | process 1 gate len = |
| process 1 gate len Δ = | | process 1 gate len Δ = | ||
| process 1 cpp = 112.5 nm | | process 1 cpp = 112.5 nm | ||
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| process 1 mmp = 112.5 nm | | process 1 mmp = 112.5 nm | ||
| process 1 mmp Δ = 0.70x | | process 1 mmp Δ = 0.70x | ||
− | | process 1 sram hp = 0. | + | | process 1 sram hp = 0.148 µm2 |
− | | process 1 sram hp Δ = | + | | process 1 sram hp Δ = 0.43x |
− | | process 1 sram hd = 0. | + | | process 1 sram hd = 0.199 µm2 |
| process 1 sram hd Δ = | | process 1 sram hd Δ = | ||
− | | process 1 sram lv = 0.171 | + | | process 1 sram lv = 0.171 µm2 |
− | | process 1 sram lv Δ = | + | | process 1 sram lv Δ = 0.45x |
| process 1 dram = | | process 1 dram = | ||
| process 1 dram Δ = | | process 1 dram Δ = | ||
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}} | }} | ||
+ | |||
+ | {{scrolling table/top|style=text-align: right; | first=Fab | ||
+ | |Process Name | ||
+ | |1st Production | ||
+ | |Type | ||
+ | |Wafer | ||
+ | | | ||
+ | |Contacted Gate Pitch | ||
+ | |Interconnect Pitch (M1P) | ||
+ | |SRAM bit cell (HD) | ||
+ | |SRAM bit cell (HS) | ||
+ | |SRAM bit cell (LP) | ||
+ | |DRAM bit cell | ||
+ | }} | ||
+ | {{scrolling table/mid}} | ||
+ | |- | ||
+ | ! colspan="2" | Common Platform <info>[[IBM]], [[Freescale]], [[AMD]]</info> !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Toshiba]] / NEC !! colspan="2" | Common Platform 2<info>[[IBM]], [[STMicroelectronics]], [[Frescale]], [[Chartered]], [[Infineon]]</info> | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | || colspan="2" | || colspan="2" | 32LP || colspan="2" | || colspan="2" | | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2010 | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | PDSOI || colspan="10" | Bulk | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="12" | 300mm | ||
+ | |- | ||
+ | ! Value !! [[45 nm]] Δ !! Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[45 nm]] Δ | ||
+ | |- | ||
+ | | 130 nm || 0.68x || 130 nm || 0.80x || 126 nm || 0.98x || 120 nm || 0.71x || 126 nm || 0.66x | ||
+ | |- | ||
+ | | ? nm || ?x || 100 nm || 0.83x || 100 nm || 0.85x || ? nm || ?x || 100 nm || ?x | ||
+ | |- | ||
+ | | 0.15 µm<sup>2</sup> || 0.41x || 0.15 µm<sup>2</sup> || 0.62x || 0.149 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || 0.64x || 0.157 µm<sup>2</sup> || 0.42x | ||
+ | |- | ||
+ | | || || || || || || || || || | ||
+ | |- | ||
+ | | || || || || || || || || || | ||
+ | |- | ||
+ | | 0.039 µm<sup>2</sup> || 0.58x | ||
+ | {{scrolling table/end}} | ||
=== Design Rules === | === Design Rules === | ||
{| class="wikitable collapsible collapsed" | {| class="wikitable collapsible collapsed" | ||
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! Layer !! Pitch !! Thick !! Aspect Ratio !! Image | ! Layer !! Pitch !! Thick !! Aspect Ratio !! Image | ||
|- | |- | ||
− | | Isolation || 140 nm || 200 || - || rowspan=" | + | | Isolation || 140 nm || 200 || - || rowspan="11" | [[file:intel 32nm design rules.png|750px]] |
|- | |- | ||
| Contacted Gate || 112.5 nm || 35 nm || -- | | Contacted Gate || 112.5 nm || 35 nm || -- | ||
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|- | |- | ||
| Metal 9 || 19.4 µm || 8 µm || 1.5 | | Metal 9 || 19.4 µm || 8 µm || 1.5 | ||
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|} | |} | ||
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== 32 nm Microarchitectures == | == 32 nm Microarchitectures == | ||
+ | * Intel | ||
+ | ** {{intel|smicroarchitectures/saltwell|Saltwell}} | ||
+ | ** {{intel|microarchitectures/sandy_bridge|Sandy Bridge}} | ||
+ | ** {{intel|microarchitectures/westmere|Westmere}} | ||
* AMD | * AMD | ||
− | ** {{amd|Bulldozer | + | ** {{amd|microarchitectures/bulldozer|Bulldozer}} |
− | ** {{amd|Piledriver | + | ** {{amd|microarchitectures/piledriver|Piledriver}} |
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{{expand list}} | {{expand list}} | ||
− | == | + | == References == |
* [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]] | * [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]] | ||
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* Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008. | * Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008. | ||
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