From WikiChip
Editing 32 nm lithography process

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 3: Line 3:
  
 
== Industry ==
 
== Industry ==
TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patterning]].
+
TSMC cancelled its planned 32nm node process.
 
+
{{scrolling table/top|style=text-align: right; | first=Fab
{{nodes comp
+
  |Process Name
<!-- Intel -->
+
  |1st Production
| process 1 fab          = [[Intel]]
+
  |Type
| process 1 name        = P1268 (CPU) / P1269 (SoC)
+
  |Wafer
| process 1 date        = 2009
+
  |&nbsp;
| process 1 lith        = 193 nm
+
  |Contacted Gate Pitch
| process 1 immersion    = Yes
+
  |Interconnect Pitch (M1P)
| process 1 exposure    = DP
+
  |SRAM bit cell
| process 1 wafer type  = Bulk
+
  |DRAM bit cell
| process 1 wafer size  = 300 mm
 
| process 1 transistor  = Planar
 
| process 1 volt        = 1 V, 0.75 V
 
| process 1 layers      = 9
 
| process 1 delta from  = [[45 nm]] Δ
 
| process 1 gate len    = 30 nm
 
| process 1 gate len Δ  = &nbsp;
 
| process 1 cpp          = 112.5 nm
 
| process 1 cpp Δ        = 0.63x
 
| process 1 mmp          = 112.5 nm
 
| process 1 mmp Δ        = 0.70x
 
| process 1 sram hp      = 0.199 µm²
 
| process 1 sram hp Δ    = &nbsp;
 
| process 1 sram hd      = 0.148 µm²
 
| process 1 sram hd Δ    = &nbsp;
 
| process 1 sram lv      = 0.171 µm²
 
| process 1 sram lv Δ    = &nbsp;
 
| process 1 dram        = &nbsp;
 
| process 1 dram Δ      = &nbsp;
 
<!-- TSMC -->
 
| process 2 fab          = [[TSMC]]
 
| process 2 name        = &nbsp;
 
| process 2 date        = &nbsp;
 
  | process 2 lith        = 193 nm
 
  | process 2 immersion    = Yes
 
  | process 2 exposure    = DP
 
  | process 2 wafer type  = Bulk
 
  | process 2 wafer size  = 300 mm
 
| process 2 transistor  = Planar
 
| process 2 volt        = 1.1 V
 
| process 2 layers      = &nbsp;
 
  | process 2 delta from  = [[40 nm]] Δ
 
  | process 2 gate len    = 30 nm
 
| process 2 gate len Δ  = &nbsp;
 
| process 2 cpp          = 130 nm
 
| process 2 cpp Δ        = &nbsp;
 
| process 2 mmp          = 100 nm
 
| process 2 mmp Δ        = &nbsp;
 
| process 2 sram hp      = &nbsp;
 
| process 2 sram hp Δ    = &nbsp;
 
| process 2 sram hd      = 0.15 µm²
 
| process 2 sram hd Δ    = &nbsp;
 
| process 2 sram lv      = &nbsp;
 
| process 2 sram lv Δ    = &nbsp;
 
| process 2 dram        = &nbsp;
 
| process 2 dram Δ      = &nbsp;
 
<!-- IBM -->
 
| process 3 fab          = [[Common Platform Alliance]]<info>The Common Platform Alliance 20 nm node was a collaboration between [[IBM]], [[Samsung]], [[Freescale]], [[Toshiba]], [[Chartered Semiconductor Manufacturing]], [[Infineon Technologies ]]</info>
 
| process 3 name        = &nbsp;
 
| process 3 date        = 2011
 
| process 3 lith        = 193 nm
 
| process 3 immersion    = Yes
 
| process 3 exposure    = DP
 
| process 3 wafer type  = Bulk
 
| process 3 wafer size  = 300 mm
 
| process 3 transistor  = Planar
 
| process 3 volt        = 1 V, 0.8 V
 
| process 3 layers      = 11
 
| process 3 delta from  = [[45 nm]] Δ
 
| process 3 gate len    = 30 nm
 
| process 3 gate len Δ  = &nbsp;
 
| process 3 cpp          = 126 nm
 
| process 3 cpp Δ        = &nbsp;
 
| process 3 mmp          = 100 nm
 
| process 3 mmp Δ        = &nbsp;
 
| process 3 sram hp      = &nbsp;
 
| process 3 sram hp Δ    = &nbsp;
 
| process 3 sram hd      = 0.157 µm²
 
| process 3 sram hd Δ    = &nbsp;
 
| process 3 sram lv      = &nbsp;
 
| process 3 sram lv Δ    = &nbsp;
 
| process 3 dram        = &nbsp;
 
| process 3 dram Δ      = &nbsp;
 
<!-- Toshiba -->
 
| process 4 fab          = [[Toshiba]] / [[NEC]]
 
| process 4 name        = &nbsp;
 
| process 4 date        = &nbsp;
 
| process 4 lith        = 193 nm
 
| process 4 immersion    = Yes
 
| process 4 exposure    = DP
 
| process 4 wafer type  = Bulk
 
| process 4 wafer size  = 300 mm
 
| process 4 transistor  = Planar
 
| process 4 volt        = 1 V
 
| process 4 layers      = &nbsp;
 
| process 4 delta from  = [[40 nm]] Δ
 
| process 4 gate len    = &nbsp;
 
| process 4 gate len Δ  = &nbsp;
 
| process 4 cpp          = 120 nm
 
| process 4 cpp Δ        = &nbsp;
 
| process 4 mmp          = 100 nm
 
| process 4 mmp Δ        = &nbsp;
 
| process 4 sram hp      = &nbsp;
 
| process 4 sram hp Δ    = &nbsp;
 
| process 4 sram hd      = 0.124 µm²
 
| process 4 sram hd Δ    = &nbsp;
 
| process 4 sram lv      = &nbsp;
 
| process 4 sram lv Δ    = &nbsp;
 
| process 4 dram        = &nbsp;
 
| process 4 dram Δ      = &nbsp;
 
<!-- IBM SOI -->
 
| process 5 fab          = [[Common Platform Alliance]] (SOI)<info>[[IBM]], [[Freescale]], [[AMD]]</info>
 
| process 5 name        = &nbsp;
 
| process 5 date        = &nbsp;
 
  | process 5 lith        = 193 nm
 
  | process 5 immersion    = Yes
 
| process 5 exposure    = DP
 
| process 5 wafer type  = SOI
 
| process 5 wafer size  = 300 mm
 
| process 5 transistor  = Planar
 
| process 5 volt        = 1 V
 
| process 5 layers      = 11
 
| process 5 delta from  = [[45 nm]] Δ
 
| process 5 gate len    = 25 nm
 
| process 5 gate len Δ  = &nbsp;
 
| process 5 cpp          = 130 nm
 
| process 5 cpp Δ        = &nbsp;
 
| process 5 mmp          = 100 nm
 
| process 5 mmp Δ        = &nbsp;
 
| process 5 sram hp      = &nbsp;
 
| process 5 sram hp Δ    = &nbsp;
 
| process 5 sram hd      = 0.149 µm²
 
| process 5 sram hd Δ    = &nbsp;
 
| process 5 sram lv      = &nbsp;
 
| process 5 sram lv Δ    = &nbsp;
 
| process 5 dram        = 0.039 µm²
 
| process 5 dram Δ      = &nbsp;
 
 
}}
 
}}
 
+
{{scrolling table/mid}}
 +
|-
 +
! colspan="2" | Common Platform <info>[[IBM]], [[Freescale]], [[AMD]]</info> !! colspan="2" | [[Intel]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Toshiba]] / NEC !! colspan="2" | Common Platform 2<info>[[IBM]], [[STMicroelectronics]], [[Frescale]], [[Chartered]], [[Infineon]]</info>
 +
|- style="text-align: center;"
 +
| colspan="2" | || colspan="2" | P1268 || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" |
 +
|- style="text-align: center;"
 +
| colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2009 || colspan="2" | 2010
 +
|- style="text-align: center;"
 +
| colspan="2" | PDSOI || colspan="10" | Bulk
 +
|- style="text-align: center;"
 +
| colspan="12" | 300mm
 +
|-
 +
! Value !! [[45 nm]] Δ !! Value !! [[45 nm]] Δ !! Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[40 nm]] Δ || Value !! [[45 nm]] Δ
 +
|-
 +
| 130 nm || 0.68x || 112.5 nm || 0.63x || 130 nm || 0.80x || 113.4 nm || 0.88x || 120 nm || 0.71x || 126 nm || 0.66x
 +
|-
 +
| ? nm || ?x || 112.5 nm || 0.70x || ? nm || ?x || 113.4 nm || 0.97x || ? nm || ?x || ?nm || ?x
 +
|-
 +
| 0.15 µm<sup>2</sup> || 0.41x || 0.171 µm<sup>2</sup> || 0.63x || 0.15 µm<sup>2</sup> || 0.62x || 0.120 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || 0.64x || 0.157 µm<sup>2</sup> || 0.42x
 +
|-
 +
| 0.039 µm<sup>2</sup> || 0.58x
 +
{{scrolling table/end}}
 
=== Design Rules ===
 
=== Design Rules ===
 
{| class="wikitable collapsible collapsed"
 
{| class="wikitable collapsible collapsed"
 
|-
 
|-
! colspan="5" | Intel 32nm Design Rules
+
! colspan="4" | Intel 32nm Design Rules
 
|-
 
|-
! Layer !! Pitch !! Thick !! Aspect Ratio !! Image
+
! Layer !! Pitch !! Thick !! Aspect Ratio
 
|-
 
|-
| Isolation || 140 nm || 200 || - || rowspan="12" | [[file:intel 32nm design rules.png|750px]]
+
| Isolation || 140 nm || 200 || -
 
|-
 
|-
 
| Contacted Gate ||  112.5 nm || 35 nm || --
 
| Contacted Gate ||  112.5 nm || 35 nm || --
Line 171: Line 65:
 
|-
 
|-
 
| Metal 9 || 19.4 µm || 8 µm || 1.5
 
| Metal 9 || 19.4 µm || 8 µm || 1.5
|-
 
| Bump || 145.9 µm || 25.5 µm || -
 
 
|}
 
|}
 
 
== Find models ==
 
== Find models ==
 
{{#ask:
 
{{#ask:
Line 205: Line 96:
 
** {{intel|Xeon E5}}
 
** {{intel|Xeon E5}}
 
** {{intel|Xeon E7}}
 
** {{intel|Xeon E7}}
 +
 +
 
* UC Davis
 
* UC Davis
 
** {{ucdavis|KiloCore}}
 
** {{ucdavis|KiloCore}}
Line 210: Line 103:
 
** {{Princeton|Piton}}
 
** {{Princeton|Piton}}
  
 +
{{expand list}}
 +
 +
== 32 nm System on Chips==
 
{{expand list}}
 
{{expand list}}
  
 
== 32 nm Microarchitectures ==
 
== 32 nm Microarchitectures ==
* AMD
+
* Intel:
** {{amd|Bulldozer|l=arch}}
+
** {{intel|Saltwell}}
** {{amd|Piledriver|l=arch}}
+
** {{intel|Sandy Bridge}}
* IBM
+
** {{intel|Westmere}}
** {{ibm|z12|l=arch}}
 
* Intel
 
** {{intel|Saltwell|l=arch}}
 
** {{intel|Sandy Bridge|l=arch}}
 
** {{intel|Westmere|l=arch}}
 
  
 
{{expand list}}
 
{{expand list}}
 
== Documents ==
 
* [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]]
 
 
== References ==
 
* Greene, B., et al. "High performance 32nm SOI CMOS with high-k/metal gate and 0.149 µm 2 SRAM and ultra low-k back end with eleven levels of copper." VLSI Technology, 2009 Symposium on. IEEE, 2009.
 
* Jan, C-H., et al. "A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
 
* Wu, Shien-Yang, et al. "A 32nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
 
* Chen, X., et al. "A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process." VLSI Technology, 2008 Symposium on. IEEE, 2008.
 
* Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
 
* Natarajan, S., et al. "A 32nm logic technology featuring 2 nd-generation high-k+ metal-gate transistors, enhanced channel strain and 0.171 μm 2 SRAM cell size in a 291Mb array." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
 
* Hasegawa, S., et al. "A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
 
* Arnaud, F., et al. "32nm general purpose bulk CMOS technology for high performance applications at low voltage." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
 
* Pilo, Harold, et al. "A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements." IEEE Journal of Solid-State Circuits 47.1 (2012): 97-106.
 
 
[[category:lithography]]
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)