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| {{lithography processes}} | | {{lithography processes}} |
− | The '''32 nanometer (32 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[40 nm lithography process|40 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 32 nm process began in 2010. This technology was superseded by the [[28 nm lithography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. | + | The '''32 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[40 nm lithography process|40 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 32 nm process began in 2010. This technology was superseded by the [[28 nm lithography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. |
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| == Industry == | | == Industry == |
− | TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patterning]].
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− | {{nodes comp
| + | === Intel === |
− | <!-- Intel -->
| + | {| class="wikitable" |
− | | process 1 fab = [[Intel]]
| + | |- |
− | | process 1 name = P1268 (CPU) / P1269 (SoC)
| + | | || Measurement || Scaling from [[45 nm]] |
− | | process 1 date = 2009
| + | |- |
− | | process 1 lith = 193 nm
| + | | Contacted Gate Pitch || 112.5 nm || 0.63x |
− | | process 1 immersion = Yes
| + | |- |
− | | process 1 exposure = DP
| + | | Interconnect Pitch (M1P) || 112.5 nm || 0.70x |
− | | process 1 wafer type = Bulk
| + | |- |
− | | process 1 wafer size = 300 mm
| + | | [[SRAM]] bit cell || 0.171 µm<sup>2</sup> || 0.63x |
− | | process 1 transistor = Planar
| + | |} |
− | | process 1 volt = 1 V, 0.75 V
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− | | process 1 layers = 9
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− | | process 1 delta from = [[45 nm]] Δ
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− | | process 1 gate len = 30 nm
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− | | process 1 gate len Δ =
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− | | process 1 cpp = 112.5 nm
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− | | process 1 cpp Δ = 0.63x
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− | | process 1 mmp = 112.5 nm
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− | | process 1 mmp Δ = 0.70x
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− | | process 1 sram hp = 0.199 µm²
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− | | process 1 sram hp Δ =
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− | | process 1 sram hd = 0.148 µm²
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− | | process 1 sram hd Δ =
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− | | process 1 sram lv = 0.171 µm²
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− | | process 1 sram lv Δ =
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− | | process 1 dram =
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− | | process 1 dram Δ =
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− | <!-- TSMC -->
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− | | process 2 fab = [[TSMC]]
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− | | process 2 name =
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− | | process 2 date =
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− | | process 2 lith = 193 nm
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− | | process 2 immersion = Yes
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− | | process 2 exposure = DP
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− | | process 2 wafer type = Bulk
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− | | process 2 wafer size = 300 mm
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− | | process 2 transistor = Planar
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− | | process 2 volt = 1.1 V
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− | | process 2 layers =
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− | | process 2 delta from = [[40 nm]] Δ
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− | | process 2 gate len = 30 nm
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− | | process 2 gate len Δ =
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− | | process 2 cpp = 130 nm
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− | | process 2 cpp Δ =
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− | | process 2 mmp = 100 nm
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− | | process 2 mmp Δ =
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− | | process 2 sram hp =
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− | | process 2 sram hp Δ =
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− | | process 2 sram hd = 0.15 µm²
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− | | process 2 sram hd Δ =
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− | | process 2 sram lv =
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− | | process 2 sram lv Δ =
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− | | process 2 dram =
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− | | process 2 dram Δ =
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− | <!-- IBM -->
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− | | process 3 fab = [[Common Platform Alliance]]<info>The Common Platform Alliance 20 nm node was a collaboration between [[IBM]], [[Samsung]], [[Freescale]], [[Toshiba]], [[Chartered Semiconductor Manufacturing]], [[Infineon Technologies ]]</info>
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− | | process 3 name =
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− | | process 3 date = 2011
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− | | process 3 lith = 193 nm
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− | | process 3 immersion = Yes
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− | | process 3 exposure = DP
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− | | process 3 wafer type = Bulk
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− | | process 3 wafer size = 300 mm
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− | | process 3 transistor = Planar
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− | | process 3 volt = 1 V, 0.8 V
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− | | process 3 layers = 11
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− | | process 3 delta from = [[45 nm]] Δ
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− | | process 3 gate len = 30 nm
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− | | process 3 gate len Δ =
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− | | process 3 cpp = 126 nm
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− | | process 3 cpp Δ =
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− | | process 3 mmp = 100 nm
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− | | process 3 mmp Δ =
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− | | process 3 sram hp =
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− | | process 3 sram hp Δ =
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− | | process 3 sram hd = 0.157 µm²
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− | | process 3 sram hd Δ =
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− | | process 3 sram lv =
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− | | process 3 sram lv Δ =
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− | | process 3 dram =
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− | | process 3 dram Δ =
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− | <!-- Toshiba --> | |
− | | process 4 fab = [[Toshiba]] / [[NEC]]
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− | | process 4 name =
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− | | process 4 date =
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− | | process 4 lith = 193 nm
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− | | process 4 immersion = Yes
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− | | process 4 exposure = DP
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− | | process 4 wafer type = Bulk
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− | | process 4 wafer size = 300 mm
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− | | process 4 transistor = Planar
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− | | process 4 volt = 1 V
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− | | process 4 layers =
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− | | process 4 delta from = [[40 nm]] Δ
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− | | process 4 gate len =
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− | | process 4 gate len Δ =
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− | | process 4 cpp = 120 nm
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− | | process 4 cpp Δ =
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− | | process 4 mmp = 100 nm
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− | | process 4 mmp Δ =
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− | | process 4 sram hp =
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− | | process 4 sram hp Δ =
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− | | process 4 sram hd = 0.124 µm²
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− | | process 4 sram hd Δ =
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− | | process 4 sram lv =
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− | | process 4 sram lv Δ =
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− | | process 4 dram =
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− | | process 4 dram Δ =
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− | <!-- IBM SOI -->
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− | | process 5 fab = [[Common Platform Alliance]] (SOI)<info>[[IBM]], [[Freescale]], [[AMD]]</info>
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− | | process 5 name =
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− | | process 5 date =
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− | | process 5 lith = 193 nm
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− | | process 5 immersion = Yes
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− | | process 5 exposure = DP
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− | | process 5 wafer type = SOI
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− | | process 5 wafer size = 300 mm
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− | | process 5 transistor = Planar
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− | | process 5 volt = 1 V
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− | | process 5 layers = 11
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− | | process 5 delta from = [[45 nm]] Δ
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− | | process 5 gate len = 25 nm
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− | | process 5 gate len Δ =
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− | | process 5 cpp = 130 nm
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− | | process 5 cpp Δ =
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− | | process 5 mmp = 100 nm
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− | | process 5 mmp Δ =
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− | | process 5 sram hp =
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− | | process 5 sram hp Δ =
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− | | process 5 sram hd = 0.149 µm²
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− | | process 5 sram hd Δ =
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− | | process 5 sram lv =
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− | | process 5 sram lv Δ =
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− | | process 5 dram = 0.039 µm²
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− | | process 5 dram Δ =
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− | }}
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| | | |
− | === Design Rules ===
| + | {| class="wikitable" |
− | {| class="wikitable collapsible collapsed" | |
| |- | | |- |
− | ! colspan="5" | Intel 32nm Design Rules | + | ! colspan="4" | Design Rules |
| |- | | |- |
− | ! Layer !! Pitch !! Thick !! Aspect Ratio !! Image | + | ! Layer !! Pitch !! Thick !! Aspect Ratio |
| |- | | |- |
− | | Isolation || 140 nm || 200 || - || rowspan="12" | [[file:intel 32nm design rules.png|750px]] | + | | Isolation || 140 nm || 200 || - |
| |- | | |- |
| | Contacted Gate || 112.5 nm || 35 nm || -- | | | Contacted Gate || 112.5 nm || 35 nm || -- |
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| |- | | |- |
| | Metal 9 || 19.4 µm || 8 µm || 1.5 | | | Metal 9 || 19.4 µm || 8 µm || 1.5 |
| + | |} |
| + | |
| + | === Samsung === |
| + | {| class="wikitable" |
| + | |- |
| + | | || Measurement |
| + | |- |
| + | | Contacted Gate Pitch || 113.4 nm |
| + | |- |
| + | | Interconnect Pitch (M1P) || 113.4 nm |
| + | |- |
| + | | [[SRAM]] bit cell || 0.120 µm<sup>2</sup> |
| + | |} |
| + | |
| + | === TSMC === |
| + | In 2010, TSMC cancelled its 32nm node process. |
| + | {| class="wikitable" |
| + | |- |
| + | | || Measurement |
| + | |- |
| + | | Contacted Gate Pitch || 130 nm |
| + | |- |
| + | | Interconnect Pitch (M1P) || ? nm |
| |- | | |- |
− | | Bump || 145.9 µm || 25.5 µm || - | + | | [[SRAM]] bit cell || 0.15 µm<sup>2</sup> |
| |} | | |} |
| | | |
− | == Find models == | + | === Toshiba / NEC === |
− | {{#ask: | + | {| class="wikitable" |
− | [[instance of::microprocessor]]
| + | |- |
− | [[process::32 nm]]
| + | | || Measurement |
− | | ?full page name
| + | |- |
− | | ?name
| + | | Contacted Gate Pitch || 120 nm |
− | | ?microprocessor family
| + | |- |
− | | ?microarchitecture
| + | | Interconnect Pitch (M1P) || ? nm |
− | | ?process
| + | |- |
− | | ?designer
| + | | [[SRAM]] bit cell || 0.124 µm<sup>2</sup> |
− | | ?manufacturer
| + | |} |
− | | ?first launched
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− | | ?base frequency
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− | | format=template|link=all|sort=name|order=asc|headers=hide|mainlabel=-|intro=<table class="wikitable"><tr><th colspan="8">[[32 nm]] Microprocessors</th></tr><tr><th colspan="3">Model</th><th colspan="5">Specs</th></tr><tr><th>Model</th><th>Family</th><th>µarch</th><th>Process</th><th>Designer</th><th>Manufacturer</th><th>Intro</th><th>Freq</th></tr>|outro=</table>|limit=0|searchlabel=Click to browse all 32 nm MPU models|sep=,|template=proc table 1|userparam=9
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− | }}
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| == 32 nm Microprocessors== | | == 32 nm Microprocessors== |
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| ** {{amd|A10}} | | ** {{amd|A10}} |
| * Intel | | * Intel |
− | ** {{intel|Celeron}}
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− | ** {{intel|Core i3}}
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− | ** {{intel|Core i5}}
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− | ** {{intel|Core i7}}
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| ** {{intel|Core i7EE}} | | ** {{intel|Core i7EE}} |
− | ** {{intel|Xeon}}
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− | ** {{intel|Xeon E3}}
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− | ** {{intel|Xeon E5}}
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− | ** {{intel|Xeon E7}}
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− | * UC Davis
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− | ** {{ucdavis|KiloCore}}
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− | * Princeton
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− | ** {{Princeton|Piton}}
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| + | {{expand list}} |
| + | |
| + | == 32 nm System on Chips== |
| {{expand list}} | | {{expand list}} |
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| == 32 nm Microarchitectures == | | == 32 nm Microarchitectures == |
− | * AMD
| + | * Intel: |
− | ** {{amd|Bulldozer|l=arch}}
| + | ** {{intel|Saltwell}} |
− | ** {{amd|Piledriver|l=arch}}
| + | ** {{intel|Sandy Bridge}} |
− | * IBM
| + | ** {{intel|Westmere}} |
− | ** {{ibm|z12|l=arch}}
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− | * Intel | |
− | ** {{intel|Saltwell|l=arch}} | |
− | ** {{intel|Sandy Bridge|l=arch}} | |
− | ** {{intel|Westmere|l=arch}} | |
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| {{expand list}} | | {{expand list}} |
− |
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− | == Documents ==
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− | * [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]]
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− |
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− | == References ==
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− | * Greene, B., et al. "High performance 32nm SOI CMOS with high-k/metal gate and 0.149 µm 2 SRAM and ultra low-k back end with eleven levels of copper." VLSI Technology, 2009 Symposium on. IEEE, 2009.
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− | * Jan, C-H., et al. "A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
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− | * Wu, Shien-Yang, et al. "A 32nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
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− | * Chen, X., et al. "A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process." VLSI Technology, 2008 Symposium on. IEEE, 2008.
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− | * Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
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− | * Natarajan, S., et al. "A 32nm logic technology featuring 2 nd-generation high-k+ metal-gate transistors, enhanced channel strain and 0.171 μm 2 SRAM cell size in a 291Mb array." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
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− | * Hasegawa, S., et al. "A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
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− | * Arnaud, F., et al. "32nm general purpose bulk CMOS technology for high performance applications at low voltage." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
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− | * Pilo, Harold, et al. "A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements." IEEE Journal of Solid-State Circuits 47.1 (2012): 97-106.
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− | [[category:lithography]]
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