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| {{lithography processes}} | | {{lithography processes}} |
− | The '''28 nanometer (28 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[32 nm lithography process|32 nm]] and [[22 nm lithography process|22 nm]] processes. Commercial [[integrated circuit]] manufacturing using 28 nm process began in 2011. This technology superseded by commercial [[22 nm lithography process|22 nm process]]. | + | The '''28 nm lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[32 nm lithography process|32 nm]] and [[22 nm lithography process|22 nm]] processes. Commercial [[integrated circuit]] manufacturing using 28 nm process began in 2011. This technology superseded by commercial [[22 nm lithography process|22 nm process]]. |
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| == Industry == | | == Industry == |
− | {{nodes comp | + | {{scrolling table/top|style=text-align: right; | first=Fab |
− | <!-- TSMC -->
| + | | |
− | | process 1 fab = [[TSMC]]
| + | |Contacted Gate Pitch |
− | | process 1 name = 28LP, 28HPL, 28HP
| + | |Interconnect Pitch (M1P) |
− | | process 1 date = 4Q 2011
| + | |SRAM bit cell (HD) |
− | | process 1 lith = 193 nm
| + | |SRAM bit cell (LP) |
− | | process 1 immersion = Yes
| + | |SRAM bit cell (HC) |
− | | process 1 exposure = DP
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− | | process 1 wafer type = Bulk
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− | | process 1 wafer size = 300 mm
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− | | process 1 transistor = Planar
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− | | process 1 volt = 1 V, 0.8 V
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− | | process 1 layers = 10
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− | | process 1 delta from = [[32 nm]] Δ
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− | | process 1 gate len = 24 nm
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− | | process 1 gate len Δ =
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− | | process 1 cpp = 117 nm
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− | | process 1 cpp Δ =
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− | | process 1 mmp = 90 nm
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− | | process 1 mmp Δ =
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− | | process 1 sram hp =
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− | | process 1 sram hp Δ =
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− | | process 1 sram hd = 0.127 µm²
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− | | process 1 sram hd Δ =
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− | | process 1 sram lv = 0.155 µm²
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− | | process 1 sram lv Δ =
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− | | process 1 dram =
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− | | process 1 dram Δ =
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− | <!-- IBM -->
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− | | process 2 fab = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[NEC]], [[STMicroelectronics]], [[Infineon Technologies]], [[Chartered Semiconductor Manufacturing]], [[Renasas]]</info>
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− | | process 2 name = 28LP, 28LPP, 28SLP
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− | | process 2 date = 2014
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− | | process 2 lith = 193 nm
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− | | process 2 immersion = Yes
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− | | process 2 exposure = DP
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− | | process 2 wafer type = Bulk
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− | | process 2 wafer size = 300 mm
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− | | process 2 transistor = Planar
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− | | process 2 volt = 1 V, 0.85 V
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− | | process 2 layers = 10
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− | | process 2 delta from = [[32 nm]] Δ
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− | | process 2 gate len = 28 nm
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− | | process 2 gate len Δ =
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− | | process 2 cpp = 113.4 nm
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− | | process 2 cpp Δ =
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− | | process 2 mmp = 90 nm
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− | | process 2 mmp Δ =
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− | | process 2 sram hp = 0.152 µm²
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− | | process 2 sram hp Δ =
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− | | process 2 sram hd = 0.120 µm²
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− | | process 2 sram hd Δ =
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− | | process 2 sram lv = 0.197 µm²
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− | | process 2 sram lv Δ =
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− | | process 2 dram =
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− | | process 2 dram Δ =
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− | <!-- UMC -->
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− | | process 3 fab = [[UMC]]
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− | | process 3 name = 28HPC, 28HLP, 28HPC+, 28µLP
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− | | process 3 date = 2013
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− | | process 3 lith = 193 nm
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− | | process 3 immersion = Yes
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− | | process 3 exposure = DP
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− | | process 3 wafer type = Bulk
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− | | process 3 wafer size = 300 mm
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− | | process 3 transistor = Planar
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− | | process 3 volt = 0.9 V, 1.05 V, 0.7 V
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− | | process 3 layers = 10
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− | | process 3 delta from = [[40 nm]] Δ
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− | | process 3 gate len = 33 nm
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− | | process 3 gate len Δ =
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− | | process 3 cpp = 120 nm
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− | | process 3 cpp Δ =
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− | | process 3 mmp = 90 nm
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− | | process 3 mmp Δ =
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− | | process 3 sram hp =
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− | | process 3 sram hp Δ =
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− | | process 3 sram hd = 0.124 µm²
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− | | process 3 sram hd Δ =
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− | | process 3 sram lv =
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− | | process 3 sram lv Δ =
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− | | process 3 dram =
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− | | process 3 dram Δ =
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− | <!-- SMIC -->
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− | | process 4 fab = [[SMIC]]
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− | | process 4 name = 28PS, 28HK, 28HKC+
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− | | process 4 date = 4Q 2013
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− | | process 4 lith =
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− | | process 4 immersion =
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− | | process 4 exposure =
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− | | process 4 wafer type =
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− | | process 4 wafer size =
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− | | process 4 transistor =
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− | | process 4 volt = 1.8 V, 2.5 V
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− | | process 4 layers = | |
− | | process 4 delta from = | |
− | | process 4 gate len = | |
− | | process 4 gate len Δ = | |
− | | process 4 cpp = | |
− | | process 4 cpp Δ = | |
− | | process 4 mmp =
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− | | process 4 mmp Δ =
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− | | process 4 sram hp =
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− | | process 4 sram hp Δ =
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− | | process 4 sram hd =
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− | | process 4 sram hd Δ =
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− | | process 4 sram lv =
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− | | process 4 sram lv Δ =
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− | | process 4 dram =
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− | | process 4 dram Δ =
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| }} | | }} |
| + | {{scrolling table/mid}} |
| + | |- |
| + | ! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]] |
| + | |- |
| + | ! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ |
| + | |- |
| + | | 90 nm || 0.70x || 117 nm || 0.72x || ?nm || ?x || ?nm || ?x || ?nm || ?x |
| + | |- |
| + | | 96 nm || 0.82x || ?nm || ?x || ?nm || ?x || ?nm || ?x || ?nm || ?x |
| + | |- |
| + | | 0.120 µm<sup>2</sup> || ?x || 0.127 µm<sup>2</sup> || 0.52x || 0.120 µm<sup>2</sup> || ?x || 0.120 µm<sup>2</sup> || ?x || 0.124 µm<sup>2</sup> || ?x |
| + | |- |
| + | | || || 0.155 µm<sup>2</sup> || || || || 0.197 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x |
| + | |- |
| + | | || || || || || || 0.152 µm<sup>2</sup> || ?x || || |
| + | {{scrolling table/end}} |
| | | |
| == 28 nm Microprocessors == | | == 28 nm Microprocessors == |
| * AMD | | * AMD |
| ** {{amd|A8}} | | ** {{amd|A8}} |
− | ** {{amd|A10}} | + | ** {{amd|A10}} |
− | **A9
| + | {{expand list}} |
− | * HiSilicon
| + | == 28 nm System on Chips == |
− | ** {{hisil|Kirin}}
| + | * Intel |
− | * Intel (Fab'ed by [[TSMC]]) | |
| ** {{intel|Atom x3}} | | ** {{intel|Atom x3}} |
− | * MediaTek
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− | ** {{mediatek|Helio}}
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− | * Phytium
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− | ** {{phytium|FT-1500A}}
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− | * PEZY
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− | ** {{pezy|PEZY-SC}}
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− | ** {{pezy|PEZY-SCnp}}
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− | * Renesas
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− | ** {{renesas|R-Car}}
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− | * Xiaomi
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− | ** {{xiaomi|Surge}}
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| | | |
| {{expand list}} | | {{expand list}} |
− |
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− | == 28 nm Microarchitectures ==
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− | * AMD
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− | ** {{amd|Steamroller|l=arch}}
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− | ** {{amd|Excavator|l=arch}}
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− | * ARM Holdings
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− | ** {{armh|Cortex-A53|l=arch}}
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− | * Nervana
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− | ** {{nervana|Lake Crest|l=arch}}
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− | * Movidius
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− | ** {{movidius|SHAVE v3.0|l=arch}}
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− | * Phytium
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− | ** {{phytium|Xiaomi|l=arch}}
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− | ** {{phytium|Mars I|l=arch}}
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− | * VIA Technologies
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− | ** {{via|Isaiah II|l=arch}}
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− | * Zhaoxin
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− | ** {{zhaoxin|ZhangJiang|l=arch}}
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− | ** {{zhaoxin|WuDaoKou|l=arch}}
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− |
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− | {{expand list}}
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− |
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− | == References ==
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− | * [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]]
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− | * Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
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− | * Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
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− | * Arnaud, F., et al. "Competitive and cost effective high-k based 28nm CMOS technology for low power applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
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− | * Yuan, J., et al. "Performance elements for 28nm gate length bulk devices with gate first high-k metal gate." Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010.
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− | * Liang, C. W., et al. "A 28nm poly/SiON CMOS technology for low-power SoC applications." VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011.
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− | * James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
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− | [[category:lithography]]
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